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ADS6443IRGCT Datasheet(PDF) 10 Page - Texas Instruments

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Part # ADS6443IRGCT
Description  QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS6443IRGCT Datasheet(HTML) 10 Page - Texas Instruments

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ADS6445, ADS6444
ADS6443, ADS6442
SLAS531B – MAY 2007 – REVISED DECEMBER 2009
www.ti.com
TIMING SPECIFICATIONS
(1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF
(2), I
O = 3.5 mA,
RL = 100 Ω
(3), no internal termination, unless otherwise noted.
ADS6445
ADS6444
ADS6443
ADS6442
TEST
Fs = 125 MSPS
Fs = 105 MSPS
Fs = 80 MSPS
Fs = 65 MSPS
PARAMETER
UNIT
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
tJ
Aperture jitter Uncertainty in
the sampling
250
250
250
250
fs rms
instant
INTERFACE: 2-wire, DDR bit clock,
14x serialization
From data
Data setup
cross-over to
tsu
0.35
0.55
0.45
0.65
0.65
0.85
0.8
1.1
ns
time(4) (5) (6)
bit clock
cross-over
From bit clock
Data hold
cross-over to
th
0.35
0.58
0.5
0.7
0.7
0.9
0.8
1.1
ns
time(4) (5) (6)
data
cross-over
From frame
clock rising
edge
Frame setup
tsu
cross-over to
0.35
0.55
0.45
0.65
0.65
0.85
0.8
1.1
ns
time
bit clock rising
edge
cross-over
From bit clock
falling edge
Frame hold
cross-over to
th
0.35
0.58
0.5
0.7
0.7
0.9
0.8
1.1
ns
time
frame clock
falling edge
cross-over
Input clock
rising edge
Clock
tpd_cl
cross-over to
propagation
3.4
4.4
5.4
3.4
4.4
5.4
3.4
4.4
5.4
3.4
4.4
5.4
ns
k
frame clock
delay (6)
rising edge
cross-over
Bit clock
cycle-cycle
350
350
350
350
ps pp
jitter (5)
Frame clock
cycle-cycle
75
75
75
75
ps pp
jitter (5)
Below specifications apply for 5 MSPS
≤ Fs ≤ 125 MSPS and
all interface options.
Delay from
input clock
Aperture
rising edge to
tA
1
2
3
1
2
3
1
2
3
1
2
3
ns
delay
the actual
sampling
instant
Aperture
Channel-
delay
channel within
–250
±80
250
–250
±80
250
–250
±80
250
–250
±80
250
ps
variation
same device
(1)
Timing parameters are ensured by design and characterization and not tested in production.
(2)
CL is the external single-ended load capacitance between each output pin and ground.
(3)
Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.
(4)
Timing parameters are measured at the end of a 2 inch pcb trace (100-
Ω characteristic impedance) terminated by RLand CL.
(5)
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6)
Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
10
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442


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