ADS7871

SLAS370C − APRIL 2002 − REVISED OCTOBER 2004

www.ti.com

3

ELECTRICAL CHARACTERISTICS

For the Total System (1), −40

°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Input

Input voltage (LNx inputs)

Linear operation

−0.2

VDD + 0.2

V

Input capacitance (2)

4

9.7

pF

Input impedance (2)

Common mode

6

M

Ω

Input impedance (2)

Differential

7

M

Ω

Channel-to-channel crosstalk

VI = 2 VPP, 60 Hz (3)

100

dB

Maximum leakage current

100

pA

Static Accuracy

Resolution

14

Bits

No missing codes

G = 1 to 20 V/V

13

Bits

Integral linearity

G = 1 to 20 V/V

−4

±2

4

LSB

Differential linearity

G = 1 to 20 V/V

−2

±0.5

4

LSB

Offset error

G = 1 to 20 V/V

−24

±1

24

LSB

Ratiometric configuration or

(4)

G = 1 to 10 V/V

−0.2

0.2

%FSR

Full-scale gain error

Ratiometric configuration or

external reference (4)

G = 16 and 20 V/V

−0.25

0.25

%FSR

Full-scale gain error

Internal reference

G = 1 to 10 V/V

−0.35

0.35

%FSR

Internal reference

G = 16 and 20 V/V

−0.4

0.4

%FSR

DC common-mode rejection ratio, RTI

VI = −0.2 V to 5.2 V, G = 20 V/V

80

dB

Power supply rejection ratio, RTI

VDD = 5 V ±10%, G = 20 V/V

88

dB

Dynamic Characteristics

Throughput rate

Continuous mode

One channel

48

ksample/s

Throughput rate

Address mode

Different channels

48

ksample/s

External clock, CCLK (5)

0.1

20

MHz

Internal oscillator frequency

2.5

MHz

Serial interface clock, SCLK

20

MHz

Data setup time

10

ns

Data hold time

10

ns

Digital Inputs

Low-level input voltage, VIL

0.8

V

High-level input voltage, VIH

VDD ≤ 3.6 V

2

V

Logic levels

High-level input voltage, VIH

VDD > 3.6 V

3

V

Logic levels

Low-level input current, IIL

1

A

High-level input current, IIH

1

µA

(1) The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate

the performance of the individual functions in the ADS7871.

(2) The ADS7871 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that

the input capacitance at any selected LNx pin changes during the conversion cycle.

(3) One channel on with its inputs grounded. All other channels off with sinewave voltage applied to their inputs.

(4) Ratiometric configuration exists when the input source is configured such that changes in the reference cause corresponding changes in the input

voltage. The same accuracy applies when a perfect external reference is used.

(5) The CCLK is divided by the DF value specified by the contents of register 3, A/D Control register, bits D0 and D1 to produce DCLK. The maximum

value of DCLK is 2.5 MHz.