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ADCS7477AIMFX Datasheet(PDF) 8 Page - Texas Instruments |
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ADCS7477AIMFX Datasheet(HTML) 8 Page - Texas Instruments |
8 / 30 page ADCS7476, ADCS7477, ADCS7478 SNAS192F – APRIL 2003 – REVISED MARCH 2013 www.ti.com ADCS7476/ADCS7477/ADCS7478 Specifications (1) ADCS7478 Converter Electrical Characteristics (continued) The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted. Boldface limits apply for TA = −40°C to +85°C: all other limits TA = 25°C, unless otherwise noted. Symbol Parameter Conditions Typical Limits Units ISOURCE = 200 µA, VOH Output High Voltage VDD −0.2 V (min) VDD = +2.7V to +5.25V VOL Output Low Voltage ISINK = 200 µA 0.4 V (max) IOL TRI-STATE Leakage Current ±10 µA (max) COUT TRI-STATE Output Capacitance 2 4 pF (max) Output Coding Straight (Natural) Binary AC ELECTRICAL CHARACTERISTICS fSCLK Clock Frequency 20 MHz (max) 40 % (min) DC SCLK Duty Cycle 60 % (max) tTH Track/Hold Acquisition Time 400 ns (max) fRATE Throughput Rate See Applications Information 1 MSPS (min) tAD Aperture Delay 3 ns tAJ Aperture Jitter 30 ps Figure 2. Timing Test Circuit Timing Test Circuit ADCS7476/ADCS7477/ADCS7478 Timing Specifications The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, Boldface limits apply for TA = −40°C to +85°C: all other limits TA = 25°C, unless otherwise noted. (1) Symbol Parameter Conditions Typical Limits Units tCONVERT 16 x tSCLK tQUIET (2) 50 ns (min) t1 Minimum CS Pulse Width 10 ns (min) t2 CS to SCLK Setup Time 10 ns (min) Delay from CS Until SDATA TRI-STATE t3 20 ns (max) Disabled (3) VDD = +2.7 to +3.6 40 ns (max) Data Access Time after SCLK Falling t4 Edge(4) VDD = +4.75 to +5.25 20 ns (max) 0.4 x t5 SCLK Low Pulse Width ns (min) tSCLK 0.4 x t6 SCLK High Pulse Width ns (min) tSCLK VDD = +2.7 to +3.6 7 ns (min) t7 SCLK to Data Valid Hold Time VDD = +4.75 to +5.25 5 ns (min) (1) All input signals are specified as tr = tf = 5 ns (10% to 90% VDD) and timed from 1.6V. (2) Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion (3) Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V. (4) Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V. 8 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: ADCS7476 ADCS7477 ADCS7478 |
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