ADC12132 datasheet(6/52 Pages) TI1

Part #	ADC12132

Description	ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold

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Manufacturer	TI1 [Texas Instruments]

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ADC12130, ADC12132, ADC12138

SNAS098G – MARCH 2000 – REVISED MARCH 2013

www.ti.com

Package Thermal Resistance

Part Number

Thermal Resistance (

θJA)

ADC12130CIN

53°C/W

ADC12130CIWM

70°C/W

ADC12132CIMSA

134°C/W

ADC12132CIWM

64°C/W

ADC121038CIN

40°C/W

ADC121038CIMSA

97°C/W

ADC12138CIWM

50°C/W

Some of these product/package combinations are obsolete and are shown here for reference only. Check the TI

web site for availability.

Converter Electrical Characteristics

The following specifications apply for (V

+ = V

A+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V

common-mode voltage) or (V

+ = V

A+ = VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode

voltage), VREF− = 0V, 12-bit + sign conversion mode

(1), source impedance for analog inputs, V

REF

− and V

REF

+ ≤ 25Ω, f

CK = fSK

= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other

limits TA = TJ = 25°C.

(2) (3) (4)

Units

Parameter

Test Conditions

Typical (5)

Limits (6)

(Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

12 + sign

Bits (min)

ILE

Integral Linearity Error

After Auto Cal (7) (8)

±1/2

±2

LSB (max)

DNL

Differential Non-Linearity

After Auto Cal

±1.5

LSB (max)

Positive Full-Scale Error

After Auto Cal (7) (8)

±1/2

±3.0

LSB (max)

Negative Full-Scale Error

After Auto Cal (7)(8)

±1/2

±3.0

LSB (max)

After Auto Cal (9)(8)

Offset Error

±1/2

±2

LSB (max)

VIN(+) = VIN(−) = 2.048V

(1)

The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.

Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.

(2)

Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+

or 5V below GND will not damage this device. However, errors in conversion can occur (if these diodes are forward biased by more than

50 mV) if the input voltage magnitude of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an

example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55 VDC to ensure accurate conversions.

(3)

To ensure accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass

capacitors at each V+ pin.

(4)

With the test condition for VREF (VREF+ − VREF−) given as +4.096V, the 12-bit LSB is 1.0 mV. For VREF = 2.5V, the 12-bit LSB is 610 μV.

(5)

Typical figures are at TJ = TA = 25°C and represent most likely parametric norm.

(6)

Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

(7)

Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes

through positive full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero

(see Figure 5 and Figure 6).

(8)

The ADC12130 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-

calibration process will result in a maximum repeatability uncertainty of 0.2 LSB.

(9)

The human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin.

6

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