TLV2553

SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002

3

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Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AIN0 – AIN10

1 – 9,

11, 12

I

Analog input. These 11 analog-signal inputs are internally multiplexed.

CS

15

I

Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,

DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK within a setup time.

DATA IN

17

I

Serial data input. The 4-bit serial data can be used as address selects the desired analog input channel or

test voltage to be converted next, or a command to activate other other features. The input data is presented

with the MSB (D7) first and is shifted in on the first four rising edges of the I/O CLOCK. After the four

address/command bits are read into the command register CMR, I/O CLOCK clocks the remaining four bits

of configuration in.

DATA OUT

16

O

The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS

is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state

and is driven to the logic level corresponding to the MSB(most significant bit)/LSB(least significant bit) value

of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level

corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.

EOC

19

O

Status output, used to indicate the end of conversion (EOC) to the host processor.

EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until

the conversion is complete and the data is ready for transfer.

GND

10

Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage

measurements are with respect to GND.

I/O CLOCK

18

I

Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:

1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK

with the multiplexer address available after the fourth rising edge.

2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input

begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK.

3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT. Data changes on the

falling edge of I/O CLOCK.

4. Control of the conversion is transferred to the internal state controller on the falling edge of the last

I/O CLOCK.

REF +

14

I/O

Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The

maximum analog input voltage range is determined by the difference between the voltage applied to terminals

REF+ and REF–.

REF –

13

I/O

Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–. This

pin is connected to analog ground (GND of the ADC) when internal reference is used.

VCC

20

Positive supply voltage