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ADS1247IPW Datasheet(PDF) 3 Page - Texas Instruments |
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ADS1247IPW Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 71 page  (V )(Gain) IN 2 AVSS 0.1V + + AVDD 0.1V - - (V )(Gain) IN 2 ADS1246 ADS1247 ADS1248 www.ti.com SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 ELECTRICAL CHARACTERISTICS Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at AVDD = +5V, DVDD = +3.3V, AVSS = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted. ADS1246, ADS1247, ADS1248 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage ±VREF/PGA (1) V (VIN = ADCINP – ADCINN) Common-mode input range V Differential input current 100 pA Absolute input current See Table 7 PGA gain settings 1, 2, 4, 8, 16, 32, 64, 128 Burnout current source 0.5, 2, or 10 μA Bias voltage (AVDD + AVSS)/2 V Bias voltage output impedance 400 Ω SYSTEM PERFORMANCE Resolution No missing codes 24 Bits Data rate 5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000 SPS Differential input, end point fit, PGA = 1 Integral nonlinearity (INL) 6 15 ppm VCM = 2.5V Offset error After calibration(2) –15 15 μV Offset drift See Figure 11 to Figure 14 nV/ °C T = +25 °C, all PGAs, Gain error –0.02 ±0.005 0.02 % data rate = 40, 80, or 160SPS Gain drift See Figure 19 to Figure 22 ppm/ °C ADC conversion time Single-cycle settling Noise See Table 1 to Table 4 Normal-mode rejection See Table 9 At dc, PGA = 1 80 90 dB Common-mode rejection At dc, PGA = 32 90 125 dB AVDD/DVDD at dc, PGA = 32, Power-supply rejection 100 135 dB data rate = 80SPS VOLTAGE REFERENCE INPUT Voltage reference input 0.5 (AVDD – AVSS) – 1 V (VREF = VREFP – VREFN) Negative reference input (REFN) AVSS – 0.1 REFP – 0.5 V Positive reference input (REFP) REFN + 0.5 AVDD + 0.1 V Reference input current 30 nA ON-CHIP VOLTAGE REFERENCE Output voltage 2.038 2.048 2.058 V Output current(3) ±10 mA Load regulation 50 μV/mA TA = +25°C to +105°C 2 10 ppm/ °C Drift(4) TA = –40°C to +105°C 6 15 ppm/ °C Startup time See Table 10 μs (1) For VREF > 2.7V, the analog input differential voltage should not exceed 2.7V/PGA. (2) Offset calibration on the order of noise. (3) Do not exceed this loading on the internal voltage reference. (4) Specified by the combination of design and final production test. Copyright © 2008–2011, Texas Instruments Incorporated 3 |
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