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ADS1292IPBSR Datasheet(PDF) 10 Page - Texas Instruments |
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ADS1292IPBSR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 75 page  1 CS SCLK DIN DOUT 2 3 8 1 2 8 3 t CSSC t DIST t DIHD t CSH t DOPD t SPWH t SPWL t SCCS Hi-Z t CSDOZ t CSDOD Hi-Z t SCLK t SDECODE CLK t CLK ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com TIMING CHARACTERISTICS NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing Timing Requirements For Figure 1(1) 2.7 V ≤ DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2 V PARAMETER DESCRIPTION MIN TYP MAX MIN TYP MAX UNIT Master clock period (CLK_DIV bit of LOFF_STAT register = 0) 1775 2170 1775 2170 ns tCLK Master clock period (CLK_DIV bit of LOFF_STAT register = 1) 444 542 444 542 ns tCSSC CS low to first SCLK, setup time 6 17 ns tSCLK SCLK period 50 66.6 ns tSPWH, L SCLK pulse width, high and low 15 25 ns tDIST DIN valid to SCLK falling edge: setup time 10 10 ns tDIHD Valid DIN after SCLK falling edge: hold time 10 11 ns tDOPD SCLK rising edge to DOUT valid 12 22 ns tCSH CS high pulse 2 2 tCLKs tCSDOD CS low to DOUT driven 10 20 ns tSCCS Eighth SCLK falling edge to CS high 3 3 tCLKs tSDECODE Command decode time 4 4 tCLKs tCSDOZ CS high to DOUT Hi-Z 10 20 ns (1) Specifications apply from –40°C to +85°C. Load on DOUT = 20 pF || 100 kΩ. 10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: ADS1291 ADS1292 ADS1292R |
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