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ADS1216Y250G4 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS1216Y250G4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 41 page www.ti.com TIMING CHARACTERISTICS t 4 MSB (CommandorCommandandData) LSB t 5 t 1 t 3 CS SCLK (POL=0) D IN D OUT NOTE:(1)BitOrder=0. t 7 MSB (1) LSB (1) t 8 t 10 t 2 t 2 t 11 t 6 t 9 SCLK (POL=1) ADS1216 SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 SPEC DESCRIPTION MIN MAX UNITS SCLK period 4 tOSC periods t1 3 DRDY periods t2 SCLK pulse width, HIGH and LOW 200 ns t3 CS LOW to first SCLK edge; setup time 0 ns t4 DIN valid to SCLK edge; setup time 50 ns t5 Valid DIN to SCLK edge; hold time 50 ns Delay between last SCLK edge for DIN and first SCLK edge for DOUT: RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 tOSC periods t6 CSREG, CSRAMX, CSRAM 200 tOSC periods CSARAM, CSARAMX 1100 tOSC periods t7 SCLK edge to valid new DOUT 50 ns t8 SCLK edge to DOUT, hold time 0 ns Last SCLK edge to DOUT tri-state t9 6 10 tOSC periods NOTE: DOUT goes tri-state immediately when CS goes HIGH. t10 CS LOW time after final SCLK edge 16 tOSC periods Final SCLK edge of one op code until first edge SCLK of next command: RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM, 4 tOSC periods CSARAM, CSREG, SLEEP, RDATA, RDATAC, STOPC CREG, CRAM 220 tOSC periods t11 CREGA 1600 tOSC periods SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY periods SELFCAL 14 DRDY periods RESET (Command, SCLK or Pin), DSYNC 16 tOSC periods 8 Submit Documentation Feedback |
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