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ADS1224IPWRG4 Datasheet(PDF) 11 Page - Texas Instruments |
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ADS1224IPWRG4 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 33 page  ADS1224 SBAS286C − JUNE 2003 − REVISED JANUARY 2009 www.ti.com 11 allowable voltage range on VREFP and VREFN during self or self gain calibration as the reference pins must remain within the specified input range of the buffer in order to establish proper gain calibration. For best performance, VREF should be AVDD/2, but it can be raised as high as AVDD. When VREF exceeds AVDD/2, it is not possible to reach the full-scale digital output value corresponding to ±2VREF, since this requires the analog inputs to exceed the power supplies. For example, if VREF = AVDD = 5V, the positive full-scale signal is 10V. The maximum positive input signal that can be supplied before the ESD diodes turn on is when AINP = 5.1V and AINN = –0.1V, resulting in VIN = 5.2V. Therefore, it is not possible to reach the positive (or negative) full-scale readings in this configuration. The digital output codes are limited to approximately one half of the entire range. For best performance, bypass the voltage reference inputs with a 0.1 µF capacitor between VREFP and VREFN. Place the capacitor as close as possible to the pins. CLOCK INPUT (CLK) This digital input supplies the system clock to the ADS1224. The CLK frequency can be increased to speed up the data rate. CLK must be left running during normal operation. It may be turned off during Standby mode to save power, but this is not required. The CLK input may be driven with 5V logic, regardless of the DVDD or AVDD voltage. Minimize the overshoot and undershoot on CLK for the best analog performance. A small resistor in series with CLK (10 Ω to 100Ω) can often help. CLK can be generated from a number of sources including standalone crystal oscillators and microcontrollers. DATA READY/DATA OUTPUT (DRDY/DOUT) This digital output pin serves two purposes. First, it indicates when new data is ready by going LOW. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the conversion data, most significant bit (MSB) first. Data is shifted out on each subsequent SCLK rising edge. After all 24 bits have been retrieved, the pin can be forced high with an additional SCLK. It will then stay high until new data is ready. This is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval. SERIAL CLOCK INPUT (SCLK) This digital input shifts serial data out with each rising edge. As with CLK, this input may be driven with 5V logic regardless of the DVDD or AVDD voltage. There is hysteresis built into this input, but care should still be taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise-and-fall times of SCLK are less than 50ns. FREQUENCY RESPONSE The ADS1224 frequency response for fCLK = 2MHz is shown in Figure 20. The frequency response repeats at multiples of the modulator sampling frequency of 62.5kHz. The overall response is that of a low-pass filter with a −3db cutoff frequency of 31.5Hz. As shown, the ADS1224 does a good job attenuating out to 60kHz. For the best resolution, limit the input bandwidth to less than this value to keep higher frequency noise from affecting performance. Often, a simple RC filter on the ADS1224 analog inputs is all that is needed. Input Frequency (Hz) 0 −20 −40 −60 −80 −100 31250 62500 0 Figure 20. Frequency Response |
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