ADS7279IRSAT datasheet(8/51 Pages) TI1

Part #	ADS7279IRSAT

Description	LOW-POWER, 14-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

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TIMING CHARACTERISTICS

(1) (2): 5V

ADS7279

ADS7280

SBAS436A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com

All specifications typical at –40°C to +85°C and +VA = +VBD = 5V, unless otherwise noted.

ADS7279, ADS7280

PARAMETER

MIN

TYP

MAX

UNIT

External,

0.5

21

fCCLK = 1/2 fSCLK

fCCLK

Frequency, conversion clock, CCLK

MHz

Internal,

21

23

24.5

fCCLK = 1/2 fSCLK

t1

Setup time, falling edge of CS to EOC

1

CCLK

t2

Hold time, falling edge of CS to EOC

0

ns

tCL

Pulse duration, CONVST low

40

ns

t3

Hold time, falling edge of CS to EOS

20

ns

t4

Setup time, rising edge of CS to EOS

20

ns

t5

Hold time, rising edge of CS to EOS

20

ns

t6

Setup time, falling edge of CS to first falling SCLK

5

ns

tSCLKL

Pulse duration, SCLK low

8

tSCLK – 8

ns

tSCLKH

Pulse duration, SCLK high

8

tSCLK – 8

ns

I/O clock only

20

I/O and conversion clock

23.8

2000

tSCLK

Cycle time, SCLK

ns

I/O clock, chain mode

20

I/O and conversion clock,

23.8

2000

chain mode

tH2

Hold time, falling edge of SCLK to SDO invalid

10pF load

2

ns

tD1

Delay time, falling edge of SCLK to SDO valid

10pF load

10

ns

Delay time, falling edge of CS to SDO valid, SDO

tD2

10pF load

8.5

ns

MSB output

tS1

Setup time, SDI to falling edge of SCLK

8

ns

tH1

Hold time, SDI to falling edge of SCLK

4

ns

tD3

Delay time, rising edge of CS/FS to SDO tD3 3-state

5

ns

Setup time, 16th falling edge of SCLK before rising

t7

10

ns

edge of CS/FS

(1)

All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.

(2)

See timing diagrams.

8

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