 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADS7862 Datasheet(PDF) 11 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
ADS7862 Datasheet(HTML) 11 Page - Texas Instruments |
|
|
11 / 21 page  ADS7862 11 SBAS101B www.ti.com FIGURE 9. Reading and Writing to the ADS7862 During the Same Cycle. DESCRIPTION ANALOG INPUT Full-Scale Input Span –VREF to +VREF(1) Least Significant (–VREF to +VREF)/4096(2) Bit (LSB) +Full Scale 4.99878V 0111 1111 1111 7FF Midscale 2.5V 0000 0000 0000 000 Midscale – 1 LSB 2.49878V 1111 1111 1111 FFF –Full Scale 0V 1000 0000 0000 800 NOTES: (1) –VREF to +VREF around VREF. With a 2.5V reference, this corre- sponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference. TABLE I. Ideal Input Voltages and Output Codes. DIGITAL OUTPUT BINARY TWO’S COMPLEMENT BINARY CODE HEX CODE mode. Figure 9, in conjunction with Table I, shows the basic read/write functions of the ADS7862 and highlights all of the timing specifications. Figure 10 shows a more detailed description of initiating a conversion using CONVST. Fig- ure 11 illustrates three consecutive conversions and, with the accompanying text, describes all of the read and write capabilities of the ADS7862. The Figure 11 timing diagram can be divided into three sections: (a) initiating a conversion (n – 2), (b) starting a second conversion (n – 1) while reading the data output from the previous conversion (n – 2), and (c) starting a third conversion (n) while reading both previous conversions (n – 2 and n – 1). In this sequence, Channel 0 is converted SYMBOL DESCRIPTION MIN TYP MAX UNITS tCONV Conversion Time 1.75 µs tACQ Acquisition Time 0.25 µs tCKP Clock Period 125 5000 ns tCKL Clock LOW 40 ns tCKH Clock HIGH 40 ns t1 CS to RD Setup Time 0 ns t2 CS to RD Hold Time 0 ns t3 CONVST LOW 15 ns t4 RD Pulse Width 30 ns t5 RD to Valid Data (Bus Access) 16 25 ns t6 RD to HI-Z Delay (Bus Relinquish) 10 20 ns t7 Time Between Conversion Reads 40 ns t8 Address Setup Time 250 ns t9 CONVST HIGH 20 ns t10 Address Hold Time 20 ns t11 CONVST to BUSY Propagation Delay 30 ns t12 CONVST LOW Prior to CLOCK Rising Edge 10 ns t13 CONVST LOW After CLOCK Rising Edge 5ns tF Data Fall Time 13 25 ns tR Data Rise Time 20 30 ns TIMING SPECIFICATIONS first followed by Channel 1. Channel 1 can be converted prior to Channel 0 if the user wishes by simply starting the conversion process with the A0 pin at logic HIGH (Channel 1) followed by logic LOW (Channel 0). t 12 t 13 t 3 t 9 t 11 Conversion n Conversion n – 1 Results Conversion n Results BUSY A0 CS RD DATA Conversion n + 1 1 CLOCK CONVST 2 3 4 5 14 15 16 1 2 3 4 5 14 15 16 t CONV t ACQ t 8 t 4 t 10 t 1 t 5 CHA1 CHB1 CHA0 CHB0 t 6 t 2 t 7 |
Similar Part No. - ADS7862_14 |
|
Similar Description - ADS7862_14 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
