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MBM30LV0064-PFTR Datasheet(PDF) 9 Page - Fujitsu Component Limited.

Part # MBM30LV0064-PFTR
Description  64M (8M X 8) BIT NAND-type
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Manufacturer  FUJITSU [Fujitsu Component Limited.]
Direct Link  http://edevice.fujitsu.com/fmd/en/index.html
Logo FUJITSU - Fujitsu Component Limited.

MBM30LV0064-PFTR Datasheet(HTML) 9 Page - Fujitsu Component Limited.

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MBM30LV0064
9
s
s
s
s FUNCTIONAL DESCRIPTION
READ MODE
There are three distinct commands used for the read operation: 00h, 01h, and 50h. After the command cycle,
three address cycles are used to input the starting address. Upon the rising edge of the final WE pulse, there
is a 7
µs latency in which the 528 byte page is transferred to the data register. The R/B signal may be used to
monitor the completion of the data transfer. In the read operation, the CE signal must stay “Low” after the third
address input and during Busy state. If the CE signal goes High during this period, the read operation will be
terminated and then the standby mode will be entered. Once the page of data has been loaded into the data
register, it may be clocked out with consecutive 50 ns RE pulses. Each RE pulse will automatically advance the
column address by one. Once the last column has been read, the page address will automatically increment by
one and the data register will be updated with the new page after 7
µs.
The 00h Read command will set the pointer to the first half page of the array while the 01h Read command will
set it in the second half. It may be logical to think of 00h as a command which sets A8 = 0 while 01h sets A8 =
1. The 50h command set the pointer to the spare area, consisting of columns 512 to 527. During this read mode,
A3 to A0 is used to set the starting address of the spare area. As with the 00h and 01h operations, once the
spare area page is loaded into the data register, it may be read out by RE pulses. Each RE pulse will increment
the column address until the final column (527) is reached. At this time, the pointer will be reset to column 512
while the page address is incriminated and the data register is updated. The 00h or 01h command is required
to move the pointer back into the main array area.
Read (1), (2): 00h/01h
The Read (1), (2) mode is invoked by latching the 00h or 01h command into the command register. This mode
(00h) will be automatically selected when the device powers up.
CLE
CE
WE
ALE
RE
I/O0
to I/O7
Y
X
X
R/B
00h
Data Output
Starting Address
Command 01h
0
255
511 527
(Column Address)
Page (Row)
Address
X
YY
Figure 2
Read Mode (1), (2) Operation


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