MSP430F11x

MIXED SIGNAL MICROCONTROLLER

SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

10

POST OFFICE BOX 655303

digital I/O

There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external

pins):

NOTE:

Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port

P2 are implemented.

watchdog timer

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A3 Signal Connections

Input Pin Number

Device Input Signal

Module Input Name

Module Block

Module Output Signal

Output Pin Number

13 - P1.0

TACLK

TACLK

ACLK

ACLK

Timer

NA

SMCLK

SMCLK

Timer

NA

9 - P2.1

INCLK

INCLK

14 - P1.1

TA0

CCI0A

14 - P1.1

10 - P2.2

TA0

CCI0B

CCR0

TA0

18 - P1.5

DVSS

GND

CCR0

TA0

10 - P2.2

DVCC

VCC

15 - P1.2

TA1

CCI1A

15 - P1.2

11 - P2.3

TA1

CCI1B

CCR1

TA1

19 - P1.6

DVSS

GND

CCR1

TA1

11 - P2.3

DVCC

VCC

16 - P1.3

TA2

CCI2A

16 - P1.3

ACLK (internal)

CCI2B

CCR2

TA2

20 - P1.7

DVSS

GND

CCR2

TA2

12 - P2.4

DVCC

VCC