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MSP430F1610IPMR Datasheet(PDF) 9 Page - Texas Instruments |
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MSP430F1610IPMR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 78 page  MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION P5.4/MCLK 48 I/O General-purpose digital I/O pin/main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O pin/submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O pin/auxiliary clock ACLK output P5.7/TBOUTH/ SVSOUT 51 I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B TB0 to TB6/SVS comparator output P6.0/A0 59 I/O General-purpose digital I/O pin/analog input a0 – 12-bit ADC P6.1/A1 60 I/O General-purpose digital I/O pin/analog input a1 – 12-bit ADC P6.2/A2 61 I/O General-purpose digital I/O pin/analog input a2 – 12-bit ADC P6.3/A3 2 I/O General-purpose digital I/O pin/analog input a3 – 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O pin/analog input a4 – 12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O pin/analog input a5 – 12-bit ADC P6.6/A6/DAC0 5 I/O General-purpose digital I/O pin/analog input a6 – 12-bit ADC/DAC12.0 output P6.7/A7/DAC1/ SVSIN 6 I/O General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). TCK 57 I Test clock. TCK is the clock input port for device programming test and bootstrap loader start TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal TMS 56 I Test mode select. TMS is used as an input port for device programming and test. VeREF+ 10 I Input for an external reference voltage VREF+ 7 O Output of positive terminal of the reference voltage in the ADC12 VREF−/VeREF− 11 I Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1 XT2IN 53 I Input port for crystal oscillator XT2. Only standard crystals can be connected. XT2OUT 52 O Output terminal of crystal oscillator XT2 QFN Pad NA NA QFN package pad connection to DVSS recommended (RTD package only) |
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