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MSP430FR5731 Datasheet(PDF) 11 Page - Texas Instruments |
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MSP430FR5731 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 117 page  MSP430FR5739, MSP430FR5738, MSP430FR5737, MSP430FR5736, MSP430FR5735 MSP430FR5734, MSP430FR5733, MSP430FR5732, MSP430FR5731, MSP430FR5730 www.ti.com SLAS639J – JULY 2011 – REVISED JUNE 2014 Table 4-1. Signal Descriptions (continued) TERMINAL NO. I/O (1) DESCRIPTION NAME RHA RGE DA PW YQD General-purpose digital I/O with port interrupt and wake up from LPMx.5 P2.5/TB0.0/UCA1TXD/ TB0 CCR0 capture: CCI0A input, compare: Out0 17 N/A 19 15 N/A I/O UCA1SIMO Transmit data – eUSCI_A1 UART mode, Slave in, master out – eUSCI_A1 SPI mode (not available on devices without UCSI_A1) General-purpose digital I/O with port interrupt and wake up from LPMx.5 TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices P2.6/TB1.0/UCA1RXD/ 18 N/A 20 16 N/A I/O without TB1) UCA1SOMI Receive data – eUSCI_A1 UART mode, Slave out, master in – eUSCI_A1 SPI mode (not available on devices without UCSI_A1) Test mode pin – enable JTAG pins TEST/SBWTCK (2) (3) 19 11 21 17 D5 I Spy-Bi-Wire input clock Reset input active low RST/NMI/SBWTDIO (2) (3) 20 12 22 18 D4 I/O Non-maskable interrupt input Spy-Bi-Wire data input/output General-purpose digital I/O with port interrupt and wake up from LPMx.5 TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB2) P2.0/TB2.0/UCA0TXD/ 21 13 23 19 E5 I/O Transmit data – eUSCI_A0 UART mode UCA0SIMO/TB0CLK/ACLK (4) Slave in, master out – eUSCI_A0 SPI mode TB0 clock input ACLK output General-purpose digital I/O with port interrupt and wake up from LPMx.5 TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB2) P2.1/TB2.1/UCA0RXD/ 22 14 24 20 D3 I/O UCA0SOMI/TB0.0 (4) Receive data – eUSCI_A0 UART mode Slave out, master in – eUSCI_A0 SPI mode TB0 CCR0 capture: CCI0A input, compare: Out0 General-purpose digital I/O with port interrupt and wake up from LPMx.5 TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB2) P2.2/TB2.2/UCB0CLK/ TB1.0 23 15 25 21 E4 I/O Clock signal input – eUSCI_B0 SPI slave mode, Clock signal output – eUSCI_B0 SPI master mode TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1) General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on devices P3.4/TB1.1/TB2CLK/ SMCLK 24 N/A 26 N/A N/A I/O without TB1) TB2 clock input (not available on devices without TB2 or package options PW, RGE) SMCLK output (not available on package options PW, RGE) (3) See Section 6.6 and Section 6.7 for use with BSL and JTAG functions. (4) See Section 6.6 and Section 6.7 for use with BSL and JTAG functions. Copyright © 2011–2014, Texas Instruments Incorporated Terminal Configuration and Functions 11 Submit Documentation Feedback Product Folder Links: MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 |
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