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MSP430FR5728 Datasheet(PDF) 10 Page - Texas Instruments |
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MSP430FR5728 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 115 page  MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725 MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720 SLASE35A – MAY 2014 – REVISED JUNE 2014 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NO. I/O (1) DESCRIPTION NAME RHA RGE DA PW General-purpose digital I/O with port interrupt and wake up from LPMx.5 TA1 CCR2 capture: CCI2A input, compare: Out2 P1.3/TA1.2/UCB0STE/ A3/CD3 8 4 12 8 I/O Slave transmit enable – eUSCI_B0 SPI mode Analog input A3 – ADC (not available on devices without ADC) Comparator_D input CD3 General-purpose digital I/O with port interrupt and wake up from LPMx.5 TB0 CCR1 capture: CCI1A input, compare: Out1 P1.4/TB0.1/UCA0STE/ A4/CD4 9 5 13 9 I/O Slave transmit enable – eUSCI_A0 SPI mode Analog input A4 – ADC (not available on devices without ADC) Comparator_D input CD4 General-purpose digital I/O with port interrupt and wake up from LPMx.5 TB0 CCR2 capture: CCI2A input, compare: Out2 Clock signal input – eUSCI_A0 SPI slave mode, P1.5/TB0.2/UCA0CLK/ A5/CD5 10 6 14 10 I/O Clock signal output – eUSCI_A0 SPI master mode Analog input A5 – ADC (not available on devices without ADC) Comparator_D input CD5 General-purpose digital I/O Test data output port PJ.0/TDO/TB0OUTH/ 11 7 15 11 I/O Switch all PWM outputs high impedance input – TB0 SMCLK/CD6 (2) SMCLK output Comparator_D input CD6 General-purpose digital I/O Test data input or test clock input PJ.1/TDI/TCLK/TB1OUTH/ Switch all PWM outputs high impedance input – TB1 (not available on devices 12 8 16 12 I/O MCLK/CD7 (2) without TB1) MCLK output Comparator_D input CD7 General-purpose digital I/O Test mode select PJ.2/TMS/TB2OUTH/ Switch all PWM outputs high impedance input – TB2 (not available on devices 13 9 17 13 I/O ACLK/CD8 (2) without TB2) ACLK output Comparator_D input CD8 General-purpose digital I/O PJ.3/TCK/CD9 (2) 14 10 18 14 I/O Test clock Comparator_D input CD9 General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package options PW, RGE) P4.0/TB2.0 15 N/A N/A N/A I/O TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on devices without TB2 or package options DA, PW, RGE) General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not P4.1 16 N/A N/A N/A I/O available on package options DA, PW, RGE) (2) See Section 6.7 for use with JTAG function. 10 Terminal Configuration and Functions Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720 |
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