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MSP430FR5947IRHAR Datasheet(PDF) 5 Page - Texas Instruments |
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MSP430FR5947IRHAR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 131 page  MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967 MSP430FR5959, MSP430FR5958, MSP430FR5957 MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471 www.ti.com SLAS704C – OCTOBER 2012 – REVISED JUNE 2014 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Device Comparison(1)(2) eUSCI FRAM SRAM Clock ADC12_ Comp_ Timer_ Timer_ Package Device AES BSL I/O (KB) (KB) System B E A(3) B(4) Type A(5) B(6) DCO 16 ext, 3, 3(7) MSP430FR5969 64 2 HFXT 16 ch. 7 2 1 yes UART 40 48 RGZ 2 int ch. 2, 2(8) LFXT DCO 16 ext, 3, 3(7) MSP430FR59691 64 2 HFXT 16 ch. 7 2 1 yes I2C 40 48 RGZ 2 int ch. 2, 2(8) LFXT DCO 16 ext, 3, 3(7) MSP430FR5968 48 2 HFXT 16 ch. 7 2 1 yes UART 40 48 RGZ 2 int ch. 2, 2(8) LFXT DCO 16 ext, 3, 3(7) MSP430FR5967 32 1 HFXT 16 ch. 7 2 1 yes UART 40 48 RGZ 2 int ch. 2, 2(8) LFXT 14 ext, 33 40 RHA 2 int ch. DCO 3, 3(7) MSP430FR5949 64 2 16 ch. 7 2 1 yes UART LFXT 2, 2(8) 12 ext, 31 38 DA 2 int ch. 14 ext, 33 40 RHA 2 int ch. DCO 3, 3(7) MSP430FR5948 48 2 16 ch. 7 2 1 yes UART LFXT 2, 2(8) 12 ext, 31 38 DA 2 int ch. 14 ext, 33 40 RHA 2 int ch. DCO 3, 3(7) MSP430FR5947 32 1 16 ch. 7 2 1 yes UART LFXT 2, 2(8) 12 ext, 31 38 DA 2 int ch. DCO 14 ext, 3, 3(7) MSP430FR59471 32 1 16 ch. 7 2 1 yes I2C 33 40 RHA LFXT 2 int ch. 2, 2(8) 14 ext, 33 40 RHA 2 int ch. DCO 3, 3(7) MSP430FR5959 64 2 16 ch. 7 2 1 yes UART HFXT 2, 2(8) 12 ext, 31 38 DA 2 int ch. 14 ext, 33 40 RHA 2 int ch. DCO 3, 3(7) MSP430FR5958 48 2 16 ch. 7 2 1 yes UART HFXT 2, 2(8) 12 ext, 31 38 DA 2 int ch. 14 ext, 33 40 RHA 2 int ch. DCO 3, 3(7) MSP430FR5957 32 1 16 ch. 7 2 1 yes UART HFXT 2, 2(8) 12 ext, 31 38 DA 2 int ch. (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging. (3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. (4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. (5) eUSCI_A supports UART with automatic Baud-rate detection, IrDA encode and decode, and SPI. (6) eUSCI_B supports I2C with multiple slave addresses, and SPI. (7) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs. (8) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any). Copyright © 2012–2014, Texas Instruments Incorporated Device Comparison 5 Submit Documentation Feedback Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 |
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