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MB90246APFV Datasheet(PDF) 2 Page - Fujitsu Component Limited. |
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MB90246APFV Datasheet(HTML) 2 Page - Fujitsu Component Limited. |
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2 / 100 page  2 MB90246A Series s FEATURES •Clock Operating clock can be selected from divided-by-2, 4, 8 or 32 of oscillation (at oscillation of 32 MHz, 1 MHz to 16 MHz). Minimum instruction execution time of 62.5 ns (at machine clock of 16 MHz) • CPU addressing space of 16 Mbytes Internal addressing of 24-bit External accessing can be performed by selecting 8/16-bit bus width (external bus mode) • Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) High code efficiency Enhanced precision calculation realized by the 32-bit accumulator Signed multiplication/division instruction • Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions • Enhanced execution speed 8-byte instruction queue • Enhanced interrupt function Priority levels: 8 levels External interrupt input ports: 4 ports • Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) • Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) Hardware stand-by mode Gear function •Process CMOS technology • I/O port General-purpose I/O ports (CMOS): 38 General-purpose I/O ports (TTL): 11 General-purpose I/O ports (N-ch open-drain): 8 Total: 57 •Timer Timebase timer/watchdog timer: 1 channel 8-bit PWM timer: 4 channels 16-bit re-load timer: 3 channels • 16-bit I/O timer 16-bit free-run timer: 1 channel Input capture (ICU): 2 channels • I/O simple serial interface Clock synchronized transmission can be used. • UART: 1 channel Clock asynchronized or clock synchronized serial transmission can be selectively used. • DTP/external interrupt circuit: 4 channels A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. (Continued) |
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