SN65LVCP204

SWITCHING CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

0 dB preemphasis

Intrinsic deterministic device (PREx_x = 0);

2.5 Gbps

30

ps

See Figure 8 for the test

pattern

circuit.

DJ

1.25 Gbps;

0 dB preemphasis

EQ = 1

Absolute deterministic

(PREx_x = 0);

Over 25-inch

7

ps

See Figure 8 for the test

pattern

(63,5-cm)

circuit.

FR4 trace

(5)

Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation

peak-to-peak deterministic jitter of the pattern generator driving the device.

(6)

The SN65LVCP204 built-in passive input equalizer compensates for ISI. For a 25-inch (63,5-cm) FR4 transmission line with 8-mil

(0,2-mm) trace width, the SN65LVCP204 typically reduces jitter by 60 ps from the device input to the device output.

(7)

Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP204 output. The value is a real value

measured with a bit-error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components

Table 2. Preemphasis Controls PL2, PL1, PS2, and PS1

OUTPUT

OUTPUT LEVEL IN mVpp

TYPICAL FR4

PREEMPHASIS

TRACE LENGTH

DE-EMPHASIZED

PREEMPHASIZED

LEVEL IN dB

0

0

0 dB

1200

1200

10 inches (25,4 cm) of FR4 trace

0

1

3 dB

850

1200

20 inches (50,8 cm) of FR4 trace

1

0

6 dB

600

1200

30 inches (76,2 cm) of FR4 trace

40 inches (101,6 cm) of FR4

1

1

9 dB

425

1200

trace

(1)

x = L or S

Table 3. Receive Equalization Settings

EQ

EQUALIZATION

TYPICAL TRACE

1

5 dB

25 inches (63,5 cm) of FR4

0

12 dB

43 inches (109,2 cm) of FR4

Copyright © 2009, Texas Instruments Incorporated

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