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MB86832-80PFV Datasheet(PDF) 5 Page - Fujitsu Component Limited. |
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MB86832-80PFV Datasheet(HTML) 5 Page - Fujitsu Component Limited. |
5 / 82 page MB86830 Series 5 6.Register 7.Clock gear • MB86832/833/834/835/836 : Supported • MB86831 : No supported 8.External signal *:RAS1# to RAS3# and DWE1# to DWE3# deletion. Register name MB86831/832/833/835/836 MB86834 Instruction Cache Invalidate Register (ICINVLD) Map of ASI = 0x0c, ADR = 0x00001000(Bank1) ASI = 0x0c, ADR = 0x80001000(Bank2) Map of ASI = 0x0c, ADR = 0x00008000(Bank1) ASI = 0x0c, ADR = 0x80008000(Bank2) Data Cache Invalidate Register (DCINVLD) Map of ASI = 0x0e, ADR = 0x00001000(Bank1) ASI = 0x0e, ADR = 0x80001000(Bank2) Map of ASI = 0x0e, ADR = 0x00008000(Bank1) ASI = 0x0e, ADR = 0x80008000(Bank2) Register name MB86831 MB86832 MB86833 MB86834 MB86835 MB86836 Ancillary Version Register (VER2) (00)16 (01)16 (02)16 (03)16 (04)16 (01)16 Item MB86831 MB86832 MB86833 MB86834 MB86835 MB86836 ASISEL pin function No Multiplex of ADR<31:28> and ASI<3:0> Multiplex of ADR<27:24> and ASI<3:0> Multiplex of ADR<31:28> and ASI<3:0> Multiplex of ADR<27:24> and ASI<3:0> DSU (debugging support unit) No Yes No Yes No DRAM controller 4Bank supported 4Bank supported 1Bank supported* 4Bank supported 1Bank supported* No General-purpose 16-bit timer No Wih 1ch. prescaler (Equivalent to MB86942) JTAG No Support Pull-up resistor or pull-down resistor Inclusion Inclusion No Inclusion |
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