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PT0109S-15

10/14/10

2

PT7M7803/7809-7812/7823-7825

µP Supervisor Circuits

Pin Configuration

2

1

1

2

VCC

GND

RESET

3

VCC

GND

RESET

3

SOT23-3

PT7M7803

PT7M7809

PT7M7810

4

3

1

2

VCC

RESET

GND

MR

4

3

1

2

VCC

GND

MR

RESET

PT7M7811

PT7M7812

SOT143

5

4

1

3

VCC

RESET

GND

MR

SOT23-5

PT7M7811

2NC

Pin Description

Pin

Type

Description

MR

I

Manual-Reset: (CMOS). Active low. Pull low to force a reset. Reset remains asserted for the duration of

the Reset Timeout Period after MR transitions from low to high. Leave unconnected or connected to VCC

if not used.

VCC

Power

GND

-

Ground Reference for all signals.

PFI

I

not used.

PFO

O

Power-Fail Output: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.

WDI

I

Watchdog Input (CMOS). If WDI remains high or low for the duration of the watchdog timeout period

impedance three-state buffer disables the watchdog feature. The internal watchdog timer clears whenever

reset is asserted or WDI occurs a rising or falling edge.

RESET

O

Active-Low Reset Output (Push-Pull or Open-Drain). It goes low when Vcc is below the reset

threshold. It remains low for about 200ms after one of the following occurs: Vcc rises above the reset

threshold (VRST), the watchdog triggers a reset, or MR goes from low to high.

RESET

O

The inverse of RESET, active high. Whenever RESET is high, RESET is low.

NC

-

No connection.

5

4

1

2

3

VCC

RESET

GND

MR

WDI

PT7M7823

1

2

3

VCC

RESET

GND

RESET

4

5

MR

PT7M7825

3

1

2

VCC

GND

WDI

4

5

RESET

PT7M7824

RESET

5

4

1

3

VCC

GND

MR

RESET

PT7M7812

2NC

11-0012