MB86612PFV datasheet(11/40 Pages) FUJITSU

Part #	MB86612PFV

Description	IEEE 1394 Bus Controller (for MPEG, DVC)

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Manufacturer	FUJITSU [Fujitsu Component Limited.]

Direct Link	http://edevice.fujitsu.com/fmd/en/index.html

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11

MB86612

4. Other

Pin name

I/O

Function

X0

I/O

External crystal connection pins for oscillator circuits.

X1

I

VCOIN

I

VCO input pin for internal PLL.

CHPO

O

Charge pump output pin for internal PLL.

ROP

O

Connect to GND through 4.7 k

Ω resistance.

RESET

I

Reset signal input pin.

This signal should be set to ‘0’ when the system power supply is off.

MODE0

I

Input ‘0’ for 80-series mode.

Input ‘1’ for 68-series mode.

MODE1

I

Input ‘0’ for non-multiplexed mode.

Input ‘1’ for multiplexed mode.

PMODE

I

For cable power supply, set to ‘0’ for power startup.

Set to ‘1’ when cable power supply is off or until system power is on.

PWR1 to PWR3

I

When operating from cable power supply, these pins determine the value of the

‘POWER_CLASS’ area of Self-ID packets.

When operating from system power supply, these pins correspond to the power

bit in the Self-ID-PKT-param setting register.

BUSRST

I

When the MB86612 is started from the power supply this bit determines whether

a bus reset is applied automatically.

Input ‘0’ for no bus reset.

Input ‘1’ for bus reset.

When this bit is set to ‘1’, a bus reset is executed 200

µs after the int-reset bit (bit

9) in the flag & status register (address 02h) is set to ‘1’.

LINKON

O

Link-on packet receiving detection pin. Outputs an ‘H’ signal for 1 to 2 tclk (1 to 2

cycles of the crystal oscillator input signal) when a link-0n packet is received.

When this signal is not used, leave it open.

AVDD

—

Analog power supply

AVSS

—

Analog ground

VDD

—

Digital power supply

VSS

—

Digital ground

TESTP

—

Test pin. Do not connect.

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