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MSP430FR5739 Datasheet(PDF) 5 Page - Texas Instruments |
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MSP430FR5739 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 115 page  MSP430FR5739, MSP430FR5738, MSP430FR5737, MSP430FR5736, MSP430FR5735 MSP430FR5734, MSP430FR5733, MSP430FR5732, MSP430FR5731, MSP430FR5730 www.ti.com SLAS639I – JULY 2011 – REVISED MAY 2014 3 Device Comparison Table 3-1 shows the available family members. Table 3-1. Family Members(1)(2) eUSCI System FRAM SRAM Channel A: Device Clock ADC10_B Comp_D Timer_A(3) Timer_B(4) I/O Package Channel B: (KB) (KB) UART, IrDA, (MHz) SPI, I2C SPI 32 RHA MSP430FR5739 16 1 24 12 ext, 2 int ch. 16 ch. 3, 3 3, 3, 3 2 1 30 DA 6 ext, 2 int ch. 10 ch. 17 RGE MSP430FR5738 16 1 24 8 ext, 2 int ch. 12 ch. 3, 3 3 1 1 21 PW 6 ext, 2 int ch. 10 ch. 17 YQD 32 RHA MSP430FR5737 16 1 24 - 16 ch. 3, 3 3, 3, 3 2 1 30 DA 10 ch. 17 RGE MSP430FR5736 16 1 24 - 3, 3 3 1 1 12 ch. 21 PW 32 RHA MSP430FR5735 8 1 24 12 ext, 2 int ch. 16 ch. 3, 3 3, 3, 3 2 1 30 DA 6 ext, 2 int ch. 10 ch. 17 RGE MSP430FR5734 8 1 24 3, 3 3 1 1 8 ext, 2 int ch. 12 ch. 21 PW 32 RHA MSP430FR5733 8 1 24 - 16 ch. 3, 3 3, 3, 3 2 1 30 DA 10 ch. 17 RGE MSP430FR5732 8 1 24 - 3, 3 3 1 1 12 ch. 21 PW 32 RHA MSP430FR5731 4 1 24 12 ext, 2 int ch. 16 ch. 3, 3 3, 3, 3 2 1 30 DA 6 ext, 2 int ch. 10 ch. 17 RGE MSP430FR5730 4 1 24 3, 3 3 1 1 8 ext, 2 int ch. 12 ch. 21 PW (1) For the most current package and ordering information, see the Package Option Addendum in Section 10, or see the TI web site at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging. (3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. (4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. Copyright © 2011–2014, Texas Instruments Incorporated Device Comparison 5 Submit Documentation Feedback Product Folder Links: MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 |
Similar Part No. - MSP430FR5739_14 |
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Similar Description - MSP430FR5739_14 |
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