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SRC803XR1H000P4 Datasheet(PDF) 3 Page - OPLINK Communications Inc. |
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SRC803XR1H000P4 Datasheet(HTML) 3 Page - OPLINK Communications Inc. |
3 / 4 page Application Notes Receiver Circuit: The receiver converts the incident optical power to a photocurrent via a high performance PIN photodiode.The photocurrent is converted to a voltage signal by a transimpedance amplifier. This signal is then amplified by additional gain stages and processed through a shaping filter and a comparator to generate the data to the clock recovery circuit.The clock recovery circuit uses a Phase Lock Loop (PLL) to recover the clock from the data and resamples the data to generate clean and reshaped differential DATAoutputs. Also provided are differential recovered CLOCK outputs. Both differential DATA+ and DATA- as well as CLOCK+ and CLOCK- outputs are open emitter PECL levels requiring termination (50 ohms to V CC - 2 volts or 510 ohms to GND is recommended). For optimum performance, both outputs should be terminated in the same manner, even if only one is used. The Signal Detect circuit monitors the level of the incoming optical signal and generates a logic LOW (TTL) signal when insufficient photocurrent is produced. Interface Circuit: The power supply line should be wellfiltered. The power supply should be bypassed by 0.01 or 0.1 µF ceramic chip capacitors placed as close to the receiver module as possible. If the receiver outputs drive long traces or multiple loads, the use of an ECL buffer gate to isolate the receiver from transmission line reflections is recommended. Oplink Communications, Inc. Pin Assignments (Top View) Pigtail Package DATA & CLOCK Timing Diagram All CASE pins should be grounded Dimension in inches 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CASE N/C N/C CLOCK + CLOCK - DATA+ GND GND DATA - N/C CASE N/C N/C N/C N/C GND SIGNAL DETECT - CASE SIGNAL DETECT+ V (+5 V) CC N/C: No internal connection The pigtail length from the package edge is 1.0 meter minimum, 1.1 meter typical. DATA CLOCK Set-up 3.0 < t S < 3.5 ns Hold 3.0 < t H < 3.3 ns SRC03 Series 3 R5.2008.06.18 |
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