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AFE7225 Datasheet(PDF) 2 Page - Texas Instruments |
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AFE7225 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 107 page  2-1 MUX SPI Interface, Registers and Control RX RMS / Peak Power Meter Clock Divide/Multiply INP_A_ADC 12b RX ADC B 12b TX DAC A 12b TX DAC B IOUTP_A_DAC Internal Reference 12b Aux DAC SYNC SYNC SYNC SYNC SYNC SYNC 12b RX ADC A INN_A_ADC INP_B_ADC INN_B_ADC CLKINP CLKINN IOUTN_A_DAC IOUTP_B_DAC IOUTN_B_DAC AUXDAC_A VCM AVDD3_DAC = 3 V 12b Aux DAC 12b Aux ADC AUXDAC_B AUXADC_A AUXADC_B PDN SYNC SEN SCLK SDATA SDOUT BIASJ RESET DVDD18_DAC = 1.8 V AVDD18_ADC = 1.8 V DVDD18 = 1.8 V AVDD3_AUX = 3 V DVDD18_CLK = 1.8 V SYNC SYNC SYNC SYNC SYNC 12-Bit ADC Outputs 12-Bit DAC Inputs ADC CLK DAC CLK SYNC NCO SYNC NCO SYNC Thermal Pad = Ground SYNC AFE7222 AFE7225 SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1.4 DETAILED BLOCK DIAGRAM Figure 1-1. Block Diagram of AFE7222/AFE7225 2 INTRODUCTION Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE7222 AFE7225 |
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