8

MB15F03SL

s FUNCTIONAL DESCRIPTION

The divide ratio can be calculated using the following equation:

: Output frequency of external voltage controlled oscillator (VCO)

M

: Preset divide ratio of dual modulus prescaler (8or 16 for IF-PLL, 64 or 128 for RF-PLL)

N

: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A

: Preset divide ratio of binary 7-bit swallow counter (0

≤ A ≤ 127)

: Reference oscillation frequency

R

: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

Serial Data Input

Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL

sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.

Serial data of binary data is entered through Data pin.

On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high,

the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.

Table.1 Control Bit

Shift Register Configuration

Control bit

Destination of serial data

CN1

CN2

L

L

The programmable reference counter for the IF-PLL

H

L

The programmable reference counter for the RF-PLL

L

H

The programmable counter and the swallow counter for the IF-PLL

H

H

The programmable counter and the swallow counter for the RF-PLL

Programmable Reference Counter

MSB

Data Flow

CN1,2

: Control bit

[Table. 1]

R1 to R14

: Divide ratio setting bit for the programmable reference counter (5 to 16,383)[Table. 2]

T1, 2

: Test purpose bit

[Table. 3]

CS

: Charge pump currnet select bit

[Table. 9]

X

: Dummy bits (Set “0” or “1”)

NOTE: Data input with MSB first.

123456789

10

11

12

13

14

15

16

17

18

19

20

21

22

23

C

N

1

C

N

2

T

1

T

2

R

1

R

2

R

3

R

4

R

5

R

6

R

7

R

8

R

9

R

10

R

11

R

12

R

13

R

14

C

S

XXXX

LSB