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LM25069 Datasheet(PDF) 10 Page - Texas Instruments |
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LM25069 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 30 page LOAD VIN GND GND LIVE POWER SOURCE PLUG - IN BOARD VSYS PGD OUT RS Q1 CL VOUT LM25069 +12V LM25069 Power Good UVLO/EN OVLO PWR GND TIMER PGD OUT SENSE GATE R1 Q1 RS CIN VSYS R2 R3 RPG VOUT RPWR CL CT LM25069 SNVS607D – FEBRUARY 2009 – REVISED DECEMBER 2010 www.ti.com Figure 3. Basic Application Circuit Functional Description The LM25069 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other "hot" power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is removed can also be implemented using the LM25069. In addition to a programmable current limit, the LM25069 monitors and limits the maximum power dissipation in the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current limiting or power limiting for an extended period of time results in the shutdown of the series pass device. In this event, the LM25069-1 latches off until the circuit is re-enabled by external control, while the LM25069-2 automatically restarts with defined timing. The circuit breaker function quickly switches off the series pass device upon detection of a severe over-current condition. The Power Good (PGD) output pin indicates when the output voltage is within 1.3V of the system input voltage (VSYS). Programmable under-voltage lock-out (UVLO) and over-voltage lock-out (OVLO) circuits enable the LM25069 when the system input voltage is between the desired thresholds. The typical configuration of a circuit card with LM25069 hot swap protection is shown in Figure 4. Figure 4. LM25069 Application Power Up Sequence The VIN operating range of the LM25069 is +2.9V to +17V, with a transient capability to 20V. Referring to the Block Diagram and Figure 3 and Figure 5, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal 260 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the POR threshold the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5 µA current source, and Q1 is held off by a 2 mA pull-down current at the GATE pin regardless of the VIN voltage. The insertion time delay allows ringing and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin voltage reaches 1.72V. CT is then quickly discharged by an internal 2 mA pull-down current. The GATE pin then switches on Q1 when VSYS exceeds the UVLO threshold. If VSYS is above the UVLO threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 20 µA to charge Q1’s gate capacitance. The maximum voltage at the GATE pin is limited by an internal 19.5V zener diode. 10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Links: LM25069 |
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