Electronic Components Datasheet Search |
|
DS50PCI402 Datasheet(PDF) 1 Page - Texas Instruments |
|
DS50PCI402 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 35 page DS50PCI402 www.ti.com SNLS320G – APRIL 2010 – REVISED MAY 2011 DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis Check for Samples: DS50PCI402 1 FEATURES input termination control circuitry • Automatic power management on an 2 • Input and Output signal conditioning individual lane basis via SMBus increases PCIe reach in backplanes and cables • Adjustable electrical idle detect threshold. • 0.09 UI of residual deterministic jitter at 5Gbps • Data rate optimized 3-stage equalization to 27 after 42” of FR4 (with Input EQ) dB gain • 0.11 UI of residual deterministic jitter at 5Gbps • Data rate optimized 6-level 0 to 12 dB transmit after 7m of PCIe Cable (with Input EQ) de-emphasis • 0.09 UI of residual deterministic jitter at 5Gbps • Flow-thru pinout in 10mmx5.5mm 54-pin with 28” of FR4 (with Output DE) leadless LLP package • 0.13 UI of residual deterministic jitter at 5Gbps • Single supply operation at 2.5V with 7m of PCIe Cable (with Output DE) • >6kV HBM ESD rating • Adjustable Transmit VOD 800 to 1200mVp-p • -10 to 85°C operating temperature range • Automatic and manual Receiver Detection and DESCRIPTION The DS50PCI402 is a low power, 4 lane bidirectional buffer/equalizer designed specifically for PCI Express Gen1 and Gen2 applications. The device performs both receive equalization and transmit de-emphasis, allowing maximum flexibility of physical placement within a system. The receiver is capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect medium. The transmitter de-emphasis level can be set by the user depending on the distance from the DS50PCI402 to the PCI Express endpoint. The DS50PCI402 contains PCI Express specific functions such as Transmit Idle, RX Detection, and Beacon signal pass through. The device provides automatic receive detection circuitry which controls the input termination impedance. By automatically reflecting the current load impedance seen on the outputs back to the corresponding inputs the DS50PCI402 becomes completely transparent to both the PCIe root complex and endpoint. An internal rate detection circuit is included to detect if an incoming data stream is at Gen2 data rates, and adjusts the de- emphasis on it's output accordingly. The signal conditioning provided by the device allows systems to upgrade from Gen1 data rates to Gen2 without reducing their physical reach. This is true for FR4 applications such as backplanes, as well as cable interconnect. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Similar Part No. - DS50PCI402_14 |
|
Similar Description - DS50PCI402_14 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |