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DRV8301 Datasheet(PDF) 8 Page - Texas Instruments |
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DRV8301 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 28 page DRV8301 SLOS719B – AUGUST 2011 – REVISED AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) PVDD = 6 V to 60 V, TC = 25°C, unless specified under test condition PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C PVDD = 8V–60V, Igate = 30mA, 9.5 11.5 CCP = 22nF VGX_NORM Gate driver Vgs voltage V PVDD = 8V–60V, Igate = 30mA, 9.5 11.5 CCP = 220nF PVDD = 6V–8V, Igate = 15mA, 8.8 CCP = 22nF VGX_MIN Gate driver Vgs voltage V PVDD = 6V–8V, Igate = 30mA, 8.3 CCP = 220nF Ioso1 Maximum source current setting 1, peak Vgs of FET equals to 2 V. REG 0x02 1.7 A Iosi1 Maximum sink current setting 1, peak Vgs of FET equals to 8 V. REG 0x02 2.3 A Ioso2 Source current setting 2, peak Vgs of FET equals to 2 V. REG 0x02 0.7 A Iosi2 Sink current setting 2, peak Vgs of FET equals to 8 V. REG 0x02 1 A Ioso3 Source current setting 3, peak Vgs of FET equals to 2 V. REG 0x02 0.25 A Iosi3 Sink current setting 3, peak Vgs of FET equals to 8 V. REG 0x02 0.5 A Gate output impedence during standby mode Rgate_off 1.6 2.4 k Ω when EN_GATE low (pins GH_x, GL_x) SUPPLY CURRENTS IPVDD1_STB PVDD1 supply current, standby EN_GATE is low. PVDD1 = 8V. 20 50 µA EN_GATE is high, no load on gate drive output, switching at 10 kHz, IPVDD1_OP PVDD1 supply current, operating 15 mA 100 nC gate charge IPVDD1_HIZ PVDD1 Supply current, HiZ EN_GATE is high, gate not switching 2 5 10 mA INTERNAL REGULATOR VOLTAGE PVDD = 8V - 60V 6 6.5 7 AVDD AVDD voltage V PVDD = 6V - 60V 5.5 6 DVDD DVDD voltage 3 3.3 3.6 V VOLTAGE PROTECTION PVDD falling 5.9 VPVDD_UV Under voltage protection limit, PVDD V PVDD rising 6 VGVDD_UV Under voltage protection limit, GVDD GVDD falling 8 V VGVDD_OV Over voltage protection limit, GVDD 16 V CURRENT PROTECTION, (VDS SENSING) PVDD = 8V - 60V 0.125 2.4 VDS_OC Drain-source voltage protection limit V PVDD = 6V - 8V(1) 0.125 1.491 Toc OC sensing response time 1.5 µs OCTW pin reporting pulse stretch length for OC TOC_PULSE 64 µs event (1) Reduced AVDD voltage range results in limitations on settings for over current protection. See Table 9. 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV8301 |
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