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TLV320DAC3100 Datasheet(PDF) 5 Page - Texas Instruments |
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TLV320DAC3100 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 99 page  TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 3.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD(1) Referenced to AVSS(2) 2.7 3.3 3.6 DVDD Referenced to DVSS(2) 1.65 1.8 1.95 Power-supply voltage range V HPVDD Referenced to HPVSS(2) 2.7 3.3 3.6 SPKVDD(1) Referenced to SPKVSS(2) 2.7 5.5 IOVDD Referenced to IOVSS(2) 1.1 3.3 3.6 Speaker impedance Resistance applied across class-D output pins (BTL) 4 Ω Headphone impedance AC-coupled to RL 16 Ω Analog audio full-scale input 0.70 VI AVDD = 3.3 V, single-ended VRMS voltage 7 Stereo line output load impedance AC coupled to RL 10 k Ω MCLK(3) Master clock frequency IOVDD = 3.3 V 50 MHz fSCL SCL clock frequency 400 kHz TA Operating free-air temperature –40 85 °C (1) To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level. (2) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground signals. By use of a wide trace or ground plane, ensure a low-impedance connection between HPVSS and DVSS. (3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock. 3.3 Electrical Characteristics At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL OSCILLATOR—RC_CLK Oscillator frequency 8.2 MHz VOLUME CONTROL PIN (ADC); VOL/MICDET PIN ENABLED VOL/MICDET pin configured as volume control (page 0 / register 116, bit D7 = 1 and page 0 / 0.5 × Input voltage range 0 V register 67, bit D7 = 0) AVDD Input capacitance 2 pF Volume control steps 128 Steps Microphone Bias Page 1 / register 46, bits D1–D0 = 10 2.25 2.5 2.75 Voltage output V Page 1 / register 46, bits D1–D0 = 01 2 At 4-mA load current, page 1 / register 46, bits D1–D0 = 10 (MICBIAS = 2.5 V) 5 Voltage regulation mV At 4-mA load current, page 1 / register 46, bits D1–D0 = 01 (MICBIAS = 2 V) 7 AUDIO DAC DAC Headphone Output, AC-Coupled Load = 16 Ω (Single-Ended), Driver Gain = 0 dB, Parasitic Capacitance = 30 pF Full-scale output voltage (0 dB) Output common-mode setting = 1.65 V 0.707 Vrms SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted (1) (2) 80 95 dB THD Total harmonic distortion 0-dBFS input –85 –65 dB THD+N Total harmonic distortion + noise 0-dBFS input –82 –60 dB Mute attenuation 87 dB DAC Headphone Output, AC-Coupled Load = 16 Ω (Single-Ended), Driver Gain = 0 dB, Parasitic Capacitance = 30 pF (Continued) PSRR Power-supply rejection ratio (3) Ripple on HPVDD (3.3 V) = 200 mVp-p at 1 kHz –62 dB RL = 32 Ω, THD+N ≤ –60 dB 20 PO Maximum output power mW RL = 16 Ω, THD+N ≤ –60 dB 60 (1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. (2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. (3) DAC to headphone-out PSRR measurement is calculated as PSRR = 20 × log( ΔVHPL / ΔVHPVDD). Copyright © 2010–2012, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 5 Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 |
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