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TLV320AIC3256 Datasheet(PDF) 9 Page - Texas Instruments |
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TLV320AIC3256 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 45 page TLV320AIC3256 www.ti.com SLOS630A – DECEMBER 2010 – REVISED DECEMBER 2010 Electrical Characteristics, ADC (continued) At 25°C, AVdd, DVdd, IOVdd,DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge pump disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC (Gain=40dB) Input signal level (for 0dB output) Differential Input, CM=0.9V, Channel Gain=40dB 10 mVRMS 1kHz sine wave input Differential configuration IN1L and IN1R routed to Right ADC IN2L and IN2R routed to Left ADC Device Setup Rin =10K, fs =48kHz, AOSR=128 MCLK = 256* fs PLL Disabled AGC = OFF Processing Block = PRB_R1, Power Tune = PTM_R4 ICN Idle-Channel Noise, Inputs ac-shorted to ground, input referred noise 2.8 mVRMS A-weighted(3) (4) AUDIO ADC 1kHz sine wave input 0.1 dB Single-ended configuration Rin = 20K fs = 48kHz, AOSR=128, Gain Error MCLK = 256* fs, PLL Disabled AGC = OFF, Channel Gain=0dB Processing Block = PRB_R1, Power Tune = PTM_R4, CM=0.9V 1kHz sine wave input at -3dBFS 109 dB Single-ended configuration IN1L routed to Left ADC Input Channel Separation IN1R routed to Right ADC, Rin = 20K AGC = OFF, AOSR = 128, Channel Gain=0dB, CM=0.9V 1kHz sine wave input at –3dBFS on IN2L, IN2L internally 108 dB not routed. Input Pin Crosstalk IN1L routed to Left ADC ac-coupled to ground 1kHz sine wave input at –3dBFS on IN2R, IN2R internally not routed. IN1R routed to Right ADC ac-coupled to ground Single-ended configuration Rin = 20K, AOSR=128 Channel, Gain=0dB, CM=0.9V 217Hz, 100mVpp signal on AVdd, 55 dB PSRR Single-ended configuration, Rin=20K, Channel Gain=0dB; CM=0.9V Single-Ended, Rin = 10K, PGA gain set to 0dB 0 dB Single-Ended, Rin = 10K, PGA gain set to 47.5dB 47.5 dB Single-Ended, Rin = 20K, PGA gain set to 0dB –6 dB ADC programmable gain amplifier gain Single-Ended, Rin = 20K, PGA gain set to 47.5dB 41.5 dB Single-Ended, Rin = 40K, PGA gain set to 0dB –12 dB Single-Ended, Rin = 40K, PGA gain set to 47.5dB 35.5 dB ADC programmable gain 1-kHz tone 0.5 dB amplifier step size (3) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. (4) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TLV320AIC3256 |
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