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URA_LD-20WR2 & URB_LD-20WR2

2013.11.29-A/3

Page 9 of 10

PACKAGE DIAGRAM

Special Package Series（A2S/A4S）

TEST CONFIGURATIONS

Input Reflected-Ripple Current Test Setup

Input reflected-ripple current is measured with an inductor Lin and Capacitor Cin to simulate source impedance.

DC

Cin

Lin

DC

Load

Oscilloscope

Current

Probe

Lin(4.7

µH)

Cin(220

µF, ESR < 1.0Ω at 100 KHz)

TRIM APPLICATION & TRIM RESISTANCE

Application circuit for TRIM (Part in broken line is the interior of models)

0V

Trim

+ Vo

0V

Trim

+Vo

Trim up

Trim down

Formula for resistance of Trim

u p:

a=

Vref

Vo

’-Vref

R=

T

R -a

2

d own :

a=

Vr ef

Vo

’- Vref

R=

T

R -a

1

trim up/down voltage.

(Table 1)

Vo

Parameter

3.3(VDC)

5(VDC)

9(VDC)

12(VDC)

15(VDC)

24(VDC)

R1(K

Ω)

4.801

2.883

7.5

10.971

14.497

24.872

R2(K

Ω)

2.863

2.864

2.864

2.864

2.864

2.863

R3(K

Ω)

15

10

15

17.8

17.8

20

Vref(V)

1.24

2.5

2.5

2.5

2.5

2.5

DESIGN CONSIDERATIONS

①Recommended circuit

All the URA_LD-20WR2 & URB_LD-20WR2 Series have been tested according to the following recommended testing circuit before leaving

factory (see Figure 4).

If you want to further decrease the input/output ripple, you can increasea capacitance properly or choose capacitors with low ESR, but the

greatest capacitance of its filter capacitor must less than the Max. Capacitive Load. The recommended capacitance of its filter capacitor sees

(Table 2).