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LMH0030 Datasheet(PDF) 6 Page - Texas Instruments |
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LMH0030 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 38 page  LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2). Symbol Parameter Conditions Reference Min Typ Max Units VIH Input Voltage High Level All LVCMOS 2.0 VDDIO V Inputs VIL Input Voltage Low Level VSSIO 0.8 V IIH Input Current High Level VIH = VDDIO +90 +150 µA IIL Input Current Low Level VIL = VSSIO −1 −20 µA VOH CMOS Output Voltage High IOH = −6.6 mA All LVCMOS 2.4 2.7 VDDIO V Level Outputs VOL CMOS Output Voltage Low IOL = +6.6 mA VSSIO VSSIO VSSIO V Level +0.3 +0.5V VSDO Serial Driver Output Voltage Test Circuit, Test Loads SDO, SDO 720 800 880 mVP-P Shall Apply IDD (3.3V) Power Supply Current, 3.3V VCLK = 27 MHz, NTSC color VDDIO, VDDSD Supply, Total Bar Pattern, Test Circuit, 48 65 mA Test Loads Shall Apply IDD (3.3V) Power Supply Current, 3.3V VCLK = 74.25 MHz, NTSC VDDIO, VDDSD Supply, Total color Bar Pattern, Test 66 90 mA Circuit, Test Loads Shall Apply IDD (2.5V) Power Supply Current, 2.5V VCLK = 27 MHz, NTSC color VDDD, VDDZ, Supply, Total Bar Pattern, Test Circuit, VDDPLL 66 85 mA Test Loads Shall Apply IDD (2.5V) Power Supply Current, 2.5V VCLK = 74.25 MHz, NTSC VDDD, VDDZ, Supply, Total color Bar Pattern, Test VDDPLL 85 110 mA Circuit, Test Loads Shall Apply (1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VSS = 0V. (2) Typical values are stated for VDDIO = VDDSD = +3.3V, VDDD = VDDPLL = +2.5V and TA = +25°C. AC ELECTRICAL CHARACTERISTICS Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1). Symbol Parameter Conditions Reference Min Typ Max Units fVCLK Parallel Video Clock VCLK 27 74.25 MHz Frequency DCV Video Clock Duty Cycle VCLK 45 50 55 % fACLK Ancillary Clock Frequency ACLK VCLK MHz DCA Ancillary Clock Duty ACLK 45 50 55 % Cycle tr, tf Input Clock and Data Rise 10%–90% VCLK, ACLK, DVN, 1.0 1.5 3.0 ns Time, Fall Time ADN BRSDO Serial Data Rate (2) (3)SDO, SDO 270 1,485 Mbps tr, tf Rise Time, Fall Time 20%–80%,(3) SDO, SDO 270 ps tr, tf Rise Time, Fall Time 20%–80%,(2) SDO, SDO 500 ps Output Overshoot (4) SDO, SDO 5 % (1) Typical values are stated for VDDIO = VDDSD = +3.3V, VDDD = VDDPLL = +2.5V and TA = +25°C. (2) RL = 75Ω, AC-coupled @ 270 Mbps, RREFLVL = RREFPRE = 4.75 kΩ 1%, See Test Loads and Test Circuit. (3) RL = 75Ω, AC-coupled @ 1,485 Mbps, RREFLVL = RREFPRE = 4.75 kΩ 1%, See Test Loads and Test Circuit. (4) Specification is ensured by design. 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0030 |
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