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F28M36H53B Datasheet(PDF) 1 Page - Texas Instruments |
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F28M36H53B Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 254 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014 F28M36x Concerto™ Microcontrollers 1 Device Summary 1.1 Features 1 • Master Subsystem — ARM® Cortex®-M3 • Control Subsystem — TMS320C28x 32-Bit CPU – 125 MHz – 150 MHz – Cortex-M3 Core Hardware Built-in Self-Test – C28x Core Hardware Built-in Self-Test – Embedded Memory – Embedded Memory • Up to 1MB of Flash (ECC) • Up to 512KB of Flash (ECC) • Up to 128KB of RAM (ECC or Parity) • Up to 36KB of RAM (ECC or Parity) • Up to 64KB of Shared RAM • Up to 64KB of Shared RAM • 2KB of IPC Message RAM • 2KB of IPC Message RAM – 5 Universal Asynchronous – IEEE-754 Single-Precision Floating-Point Unit Receiver/Transmitters (UARTs) (FPU) – 4 Synchronous Serial Interfaces (SSIs) – Viterbi, Complex Math, CRC Unit (VCU) and Serial Peripheral Interface (SPI) – Serial Communications Interface (SCI) – 2 Inter-integrated Circuits (I2Cs) – SPI – Universal Serial Bus On-the-Go (USB-OTG) + – I2C PHY – 6-Channel Direct Memory Access (DMA) – 10/100 ENET 1588 MII – 12 Enhanced Pulse Width Modulator (ePWM) – 2 Controller Area Networks (CANs) Modules – 32-Channel Micro Direct Memory Access • 24 Outputs (16 High-Resolution) (µDMA) – 6 32-Bit Enhanced Capture (eCAP) Modules – Dual Security Zones (128-Bit Password per – 3 32-Bit Enhanced Quadrature Encoder Pulse Zone) (eQEP) Modules – External Peripheral Interface (EPI) – Multichannel Buffered Serial Port (McBSP) – Micro Cyclic Redundancy Check (µCRC) – EPI Module – One Security Zone (128-Bit Password) – 4 General-Purpose Timers – 3 32-Bit Timers – 2 Watchdog Timer Modules – Endianness: Little Endian – Endianness: Little Endian • Analog Subsystem • Clocking – Dual 12-Bit Analog-to-Digital Converters (ADCs) – On-chip Crystal Oscillator and External Clock – Up to 2.88 MSPS Input – Up to 24 Channels – Dynamic Phase-Locked Loop (PLL) Ratio – 4 Sample-and-Hold (S/H) Circuits Changes Supported – Up to 6 Comparators With 10-Bit Digital-to- • 1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design Analog Converter (DAC) • Interprocessor Communications (IPC) • Package – 32 Handshaking Channels – 289-Ball ZWT New Fine Pitch Ball Grid Array – 4 Channels Generate IPC Interrupts (nFBGA) – Can be Used to Coordinate Transfer of Data Through IPC Message RAMs • Up to 142 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins – Glitch-free I/Os 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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