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DS125DF410 Datasheet(PDF) 1 Page - Texas Instruments |
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DS125DF410 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 45 page DS125DF410 www.ti.com SNLS398E – JANUARY 2012 – REVISED MAY 2013 DS125DF410 Low Power Multi-Rate Quad Channel Retimer Check for Samples: DS125DF410 1 FEATURES APPLICATIONS 2 • Each Channel Independently Locks to Data • Front Port SFF 8431 (SFP+) Optical and Direct Rates from 9.8 to 12.5 Gbps and Submultiples Attach Copper • Fast Lock Operation Based on Protocol-Select • Backplane Reach Extension, Data Retimer Mode • Ethernet: 10GbE, 1GbE • Low Latency (~300ps) • CPRI: Line Bit Rate Options 3–7 • Adaptive Equalization up to 34 dB Boost at 5 • Interlaken: All Lane Bit Rates GHz • InfiniBand • Adjustable Transmit VOD : 600 to 1300 mVp-p • Other Propriety Data Rates up to 12.5 Gbps • Adjustable Transmit De-emphasis to -15 dB • Typical Power Dissipation (EQ+DFE+CDR+DE): DESCRIPTION 180 mW /Channel The DS125DF410 is four channel retimer with integrated signal conditioning. The device includes a • Programmable Output Polarity Inversion fully adaptive Continuous-Time Linear Equalizer • Input Signal Detection, CDR Lock (CTLE), self calibrating 5-tap Decision Feedback Detection/Indicator Equalizer (DFE), Clock and Data Recovery (CDR), • On-Chip Eye Monitor (EOM), PRBS Generator and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired • Single 2.5 V ±5% Power Supply highspeed serial links to achieve BER < 1×10-15. • SMBus/EEPROM Configuration Modes Each channel can independently lock to data rate • Operating Temperature Range of -40 to 85°C from 9.8 to 12.5 Gbps, and associated sub rates (div • RHS (QFN) 48-Pin 7 mm x 7 mm Package by 2, 4 and 8) to support a variety of communication • Easy Pin Compatible Upgrade Between protocols. A 25 MHz crystal oscillator clock is used to Repeater and Retimers speed up the CDR lock process. This clock is not used for training the PLL and does not need to be – DS100RT410 (EQ+CDR+DE): 10.3125 Gbps synchronous with the serial data. – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 The programmable settings can be applied using the Gbps SMBus (I2C) interface, or they can be loaded via an – DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps external EEPROM. An on-chip eye monitor and a – DS110DF410 (EQ+DFE+CDR+DE): 8.5 - 11.3 PRBS generator allow real-time measurement of Gbps high-speed serial data for system bring-up or field tuning. – DS125RT410 (EQ+CDR+DE): 9.8 - 12.5 Gbps – DS125DF410 (EQ+DFE+CDR+DE): 9.8 - 12.5 The device is offered in a RHS (QFN) 48-pin, 7 mm x 7 mm package. A flow-through pinout for the high Gbps speed signals and a single power supply makes the – DS100BR410 (EQ+DE): Up to 10.3125 Gbps DS125DF410 easy to use. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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