DS99R105, DS99R106

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SNLS242D – MARCH 2007 – REVISED APRIL 2013

DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Check for Samples: DS99R105, DS99R106

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FEATURES

DESCRIPTION

The DS99R105/DS99R106 Chipset translates a 24-

2

•

3 MHz–40 MHz Clock Embedded and DC-

bit parallel bus into a fully transparent data/control

Balancing 24:1 and 1:24 Data Transmissions

LVDS serial stream with embedded clock information.

•

Capable to Drive Shielded Twisted-Pair Cable

This single serial stream simplifies transferring a 24-

•

User Selectable Clock Edge for Parallel Data

bit bus over PCB traces and cable by eliminating the

skew problems between parallel data and clock

on Both Transmitter and Receiver

paths. It saves system cost by narrowing data paths

•

Internal DC Balancing Encode/Decode –

that in turn reduce PCB layers, cable width, and

Supports AC-Coupling Interface with no

connector size and pins.

External Coding Required

The

DS99R105/DS99R106

incorporates

LVDS

•

Individual Power-Down Controls for Both

signaling on the high-speed I/O. LVDS provides a low

Transmitter and Receiver

power

and

low

noise

environment

for

reliably

•

Embedded Clock CDR (Clock and Data

transferring data over a serial transmission path. By

Recovery) on Receiver and no External Source

optimizing the serializer output edge rate for the

of Reference Clock Needed

operating frequency range EMI is further reduced.

•

All Codes RDL (Random Data Lock) to Support

In addition the device features pre-emphasis to boost

Live-Pluggable Applications

signals over longer distances using lossy cables.

Internal DC balanced encoding/decoding is used to

•

LOCK Output Flag to Ensure Data Integrity at

support AC-Coupled interconnects.

Receiver Side

•

RDATA on Receiver Side

•

PTO (Progressive Turn-On) LVCMOS Outputs

to Reduce EMI and Minimize SSO Effects

•

All LVCMOS Inputs and Control Pins have

Internal Pulldown

•

On-Chip Filters for PLLs on Transmitter and

Receiver

•

Integrated 100

Ω Input Termination on Receiver

•

4 mA Receiver Output Drive

•

48-Pin TQFP and 48-Pin WQFN Packages

•

Pure CMOS .35

μm Process

•

Power Supply Range 3.3V ± 10%

•

Temperature Range 0°C to +70°C

•

8 kV HBM ESD Tolerance

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PRODUCTION DATA information is current as of publication date.

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Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

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