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DS92LX2122 Datasheet(PDF) 11 Page - Texas Instruments |
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DS92LX2122 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 43 page  DS92LX2121, DS92LX2122 www.ti.com SNLS330J – MAY 2010 – REVISED JANUARY 2014 Serializer Electrical Characteristics Deserializer Switching Characteristics (1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units LVCMOS Low-to-High Transition VDDIO: 1.71 V to 1.89 V tCLH 1.6 2.4 3.3 Time or 3.0 V to 3.6 V, Deserializer Data CL = 8pF (lumped load) ns Outputs LVCMOS High-to-Low Transition Default Registers tCHL 1.6 2.4 3.3 Time (Figure 17) (4) tROS ROUT Setup Data to PCLK VDDIO: 1.71 V to 1.89 V 0.38 0.5 or 3.0 V to 3.6 V, CL = Deserializer Data T 8pF (lumped load) Outputs tROH ROUT Hold Data to PCLK 0.38T 0.5T Default Registers Default Registers Register 0x03h b[0] 4.571T + 4.571T + 4.571T tDD Deserializer Delay 10 MHz - 50 MHz ns (RRFB = 1) 8 12 + 16 Figure 18 tDDLT Deserializer Data Lock Time (5) 10 MHz - 50 MHz 10 ms tRJIT Receiver Input Jitter Tolerance (6) (7)50 MHz 0.53 UI PCLK 10 MHz 300 550 tDCJ Deserializer Clock Jitter SSCG[3:0] = OFF ps 50 MHz 120 250 (8) (9) PCLK 10 MHz 425 600 tDPJ Deserializer Period Jitter SSCG[3:0] = OFF ps 320 480 50 MHz (10) (9) PCLK 10 MHz 320 500 Deserializer Cycle-to-Cycle Clock tDCCJ SSCG[3:0] = OFF ps 300 500 Jitter 50 MHz (11) (9) Spread Spectrum Clocking ±0.5% to fDEV 20 MHz - 50 MHz % LVCMOS Output Bus Deviation Frequency ±2.0% SSC[3:0] = ON Spread Spectrum Clocking 9 kHz to Figure 20 fMOD 20 MHz - 50 MHz kHz Modulation Frequency 66 kHz (5) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK. (6) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. (7) tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI. (8) tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE). (9) Specification is ensured by characterization and is not tested in production. (10) tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples. (11) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples. Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I 2C Compliant (Figure 5) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units RECOMMENDED INPUT TIMING REQUIREMENTS(1) fSCL SCL Clock Frequency fSCL = 100 kHz >0 100 kHz fLOW SCL Low Period 4.7 µs fHIGH SCL High Period 4.0 µs Hold time for a start or a repeated start tHD:STA 4.0 µs condition Set Up time for a start or a repeated tSU:STA 4.7 µs start condition tHD:DAT Data Hold Time 0 3.45 µs tSU:DAT Data Set Up Time 250 ns tSU:STO Set Up Time for STOP Condition, 4.0 µs tr SCL & SDA Rise Time 1000 ns tf SCL & SDA Fall Time 300 ns Cb Capacitive load for bus 400 pF (1) Recommended Input Timing Requirements are input specifications and not tested in production. Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DS92LX2121 DS92LX2122 |
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