DS90UR910Q

SNLS414C – JUNE 2012 – REVISED MAY 2013

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AC SWITCHING CHARACTERISTICS

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

FPD-LINK II RECEIVER (RIN±)

Input Jitter Tolerance, Figure 2

EQ = OFF,

jitter freq < 2MHz

0.9

PCLK = 65MHz

jitter freq > 6MHz

0.5

UI

Deserializer Lock Time, Figure 3

PCLK = 75 MHz

10

ms

HSTX DRIVER AC SPECIFICATIONS (DATA0±, DATA1±, CLK±) Section 8.1.1 of MIPI D-PHY Specification

Data bit rate

DATA0±

PCLK = 10-

120

PCLK*12

900

Mbps

DATA1±

DDR Clock frequency

CLK±

60

PCLK*6

450

MHz

Common mode voltage variations

Common-level variations above 450

15

HF

Common mode voltage variations LF Common-level variations between

25

Rise Time HS

0.3

150

ps

Fall Time HS

0.3

150

ps

TX differential return loss

–18

dB

MIPI D-PHY

–12

dB

–6

dB

TX common mode return loss

Section 7.7.2 of

MIPI D-PHY

–6

dB

Section 8.1.2 of MIPI D-PHY Specification

Rise Time

LP 15% to 85% rise time

25

ns

Cload = 70pF lumped capacitance

Fall Time

LP 15% to 85% fall time

25

ns

Cload = 70pF lumped capacitance

Post-EoT Rise and Fall Time

35

ns

Pulse width of the LP exclusive-OR

First LP exclusive-OR clock pulse

clock

after Stop state or last pulse before

40

ns

20

ns

Period of the LP exclusive-OR clock

90

ns

(1)

UI is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.

(2)

Specification is ensured by design and is not tested in production.

(3)

Specification is ensured by characterization.

(4)

CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be

<10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.

8

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