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DS90UR910Q Datasheet(PDF) 8 Page - Texas Instruments |
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DS90UR910Q Datasheet(HTML) 8 Page - Texas Instruments |
8 / 31 page DS90UR910Q SNLS414C – JUNE 2012 – REVISED MAY 2013 www.ti.com AC SWITCHING CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units FPD-LINK II RECEIVER (RIN±) tIJT Input Jitter Tolerance, Figure 2 EQ = OFF, jitter freq < 2MHz 0.9 UI(1) PCLK = 65MHz jitter freq > 6MHz 0.5 UI tDDLT Deserializer Lock Time, Figure 3 PCLK = 75 MHz 10 ms HSTX DRIVER AC SPECIFICATIONS (DATA0±, DATA1±, CLK±) Section 8.1.1 of MIPI D-PHY Specification HSTXDBR Data bit rate DATA0± PCLK = 10- 120 PCLK*12 900 Mbps DATA1± 75MHz(2) fCLK DDR Clock frequency CLK± 60 PCLK*6 450 MHz ΔVCMTX(HF) Common mode voltage variations Common-level variations above 450 15 mVRMS HF MHz(2) ΔVCMTX(LF) Common mode voltage variations LF Common-level variations between 25 mVPEAK 50–450 MHz(2) tRHS Rise Time HS 20% to 80% rise time(3) 0.3 UIINST 150 ps tFHS Fall Time HS 20% to 80% rise time(3) 0.3 UIINST 150 ps SDDTX TX differential return loss See Figure 33 of fLPMAX –18 dB MIPI D-PHY fH –12 dB Specification(2) fMAX –6 dB SCCTX TX common mode return loss Section 7.7.2 of fLPMAX to fMAX MIPI D-PHY –6 dB Specification(2) LPTX DRIVER AC SPECIFICATIONS (DATA0±, DATA1±, CLK±)(4) Section 8.1.2 of MIPI D-PHY Specification tRLP Rise Time LP 15% to 85% rise time 25 ns Cload = 70pF lumped capacitance tFLP Fall Time LP 15% to 85% fall time 25 ns Cload = 70pF lumped capacitance tREOT Post-EoT Rise and Fall Time 30%-85% rise time and fall time(2) 35 ns tLP-PULSE-TX Pulse width of the LP exclusive-OR First LP exclusive-OR clock pulse clock after Stop state or last pulse before 40 ns Stop state(2) All other pulses(2) 20 ns tLP-PER-TX Period of the LP exclusive-OR clock See(2) 90 ns (1) UI is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency. (2) Specification is ensured by design and is not tested in production. (3) Specification is ensured by characterization. (4) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be <10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay. 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90UR910Q |
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