DS90UR910Q

SNLS414C – JUNE 2012 – REVISED MAY 2013

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PIN DESCRIPTIONS(1) (continued)

Pin Name

Pin #

I/O, Type

Description

Control and Configuration

Power Down Mode Input

PDB = 1, Device is enabled (normal operation)

I, LVCMOS

PDB

30

PDB = 0, Device is in power-down

w/ pull-down

When the device is in the power-down, outputs are TRI-STATE, control registers are

RESET.

I, LVCMOS

Operating Mode Select

CONFIG[1:0]

10, 11

w/ pull-down

CONFIG[1:0] selects compatibility to FPD-Link II serializers. See Table 1.

Receive equalization control

I, LVCMOS

EQ[3:1] provides 8 combinations of the receive equalization gain settings. See Table 2.

EQ[3:1]

1, 2, 3

w/ pull-down

EQ[3:1] optimizes the input equalizer’s ability to reduce inter-symbol interference from the

loss characteristics of different cable lengths.

BIST Enable Input

I, LVCMOS

BISTEN

29

BISTEN = 1, BIST is enabled

w/ pull-down

BISTEN = 0, BIST is disabled

LOCK Status Output

LOCK

24

O, LVCMOS

LOCK = 1, PLL acquired lock to the reference clock input; DPHY outputs are active

LOCK = 0, PLL is unlocked

Normal mode status output pin (BISTEN = 0)

PASS = 1: No fault detected on input display timing

PASS = 0: Indicates an error condition or corruption in display timing. Fault condition occurs

if:

PASS

25

O, LVCMOS

1) DE length value mismatch measured once in succession

2) VSync length value mismatch measured twice in succession

BIST mode status output pin (BISTEN = 1)

PASS = 1: No error detected

PASS = 0: Error detected

CCI / I2C Serial Control Bus

I, LVCMOS,

Serial Control Bus Clock Input

SCL

6

Open Drain

I/O, LVCMOS Serial Control Bus Data Input / Output

SDA

5

Open Drain

I, LVCMOS

Serial Control Bus Device ID Address Select

ID[1:0]

8, 9

w/ pull-down

See Table 5.

Reserved Pins

General Purpose I/O

GPIO

21

I/O

Note: Pin must be left floating during initial power-up.

I, LVCMOS

RES

28

Reserved pin. Must tie Low.

w/ pull-down

Power and Ground

VDDL

7

Power

Power to logic circuitry, 1.8V ±5%

VDDA

39

Power

Power to analog circuitry, 1.8V ±5%

VDDP

40

Power

Power to PLL, 1.8V ±5%

VDDCSI

20

Power

Power to DPHY CSI-2 drivers, 1.8V ±5%

VDDIO

23

Power

4, 14, 17,

GND

22, 27, 32,

Ground

Ground return.

36

DAP is the metal contact at the bottom side, located at the center of the WQFN package. It

should be connected to the GND plane with multiple via to lower the ground impedance and

GND

DAP

Ground

improve the thermal performance of the package. Connected to the ground plane (GND) with

at least 9 vias.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

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