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DS90UA101-Q1 Datasheet(PDF) 4 Page - Texas Instruments |
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DS90UA101-Q1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 41 page PDB VDDPLL VDDT DOUT- DOUT+ VDDCML GPO3 GPO2 DS90UA101-Q1 (Top View) DIN5 VDDIO DAP = GND DIN4 DIN2 DIN3 VDDD DIN1 DIN0 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 DS90UA101-Q1 SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com DS90UA101-Q1 Pin Diagram Figure 3. DS90UA101-Q1 — Top View Pin Descriptions Pin Name Pin # I/O, Type Description Digital Audio Interface SCK 3 Input, LVCMOS w/ System clock input. pull down Forward channel audio data is clocked from this pin. LRCK 2 Input, LVCMOS w/ Word clock input. pull down BCK 1 Input, LVCMOS w/ Bit clock input. pull down DIN[7:0] 23, 24, 26, 27, Inputs, LVCMOS Digital audio data inputs. Each input can be in I2S, TDM, LJ, or RJ format. 29, 30, 31, 32 w/ pull down LVCMOS Parallel Interface GPI[3:0] 19, 20, 21, 22 Inputs, LVCMOS General purpose inputs. w/ pull down GPO[3:0] 15, 16, 17, 18 Outputs, LVCMOS General purpose outputs. Control and Configuration SCL 4 Input/Output, Open I2C clock line. Drain Must have an external pull-up to VDDIO. DO NOT FLOAT. Recommended pull-up: 4.7 k Ω. SDA 5 Input/Output, Open I2C data input/output line. Drain Must have an external pull-up to VDDIO. DO NOT FLOAT. Recommended pull-up: 4.7 k Ω. IDx 6 Input, Analog Device I2C address select. The IDx pin on the Serializer is used to assign its I2C device address. See Table 2. DO NOT FLOAT. SET 8 Input, Analog Device SET. Connect to external 10 k Ω pull-up to 1.8V rail and 100kΩ pull-down to GND. DO NOT FLOAT. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 |
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