DS32EV400

www.ti.com

SNLS280E – AUGUST 2007 – REVISED OCTOBER 2009

PIN DESCRIPTIONS

Pin Name

Pin #

Description

HIGH SPEED DIFFERENTIAL I/O

IN_0+

1

I, CML

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100

Ω

IN_0–

2

terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 6.

IN_1+

4

I, CML

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100

Ω

IN_1–

5

terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 6.

IN_2+

8

I, CML

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100

Ω

IN_2–

9

terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 6.

IN_3+

11

I, CML

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100

Ω

IN_3–

12

terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 6.

OUT_0+

36

O, CML

Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50

Ω

OUT_0–

35

OUT_1+

33

O, CML

Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50

Ω

OUT_1–

32

OUT_2+

29

O, CML

Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50

Ω

OUT_2–

28

OUT_3+

26

O, CML

Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50

Ω

OUT_3–

25

EQUALIZATION CONTROL

BST_2

37

I, LVCMOS

BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is

BST_1

14

internally pulled high. BST_1 and BST_0 are internally pulled low.

BST_0

23

DEVICE CONTROL

EN0

44

I, LVCMOS

Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held

Low, standby mode is selected. EN is internally pulled High.

EN1

42

I, LVCMOS

Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held

Low, standby mode is selected. EN is internally pulled High.

EN2

40

I, LVCMOS

Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held

Low, standby mode is selected. EN is internally pulled High.

EN3

38

I, LVCMOS

Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held

Low, standby mode is selected. EN is internally pulled High.

FEB

21

I, LVCMOS

Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]

pins. When held low, the equalizer boost setting is controlled by SMBus (see Table 1) register

bits. FEB is internally pulled High.

SD0

45

O, LVCMOS

Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.

SD1

43

O, LVCMOS

Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.

SD2

41

O, LVCMOS

Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.

SD3

39

O, LVCMOS

Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.

POWER

3, 6, 7,

Power

10, 13,

15, 46

GND

22, 24,

Power

Ground reference. GND should be tied to a solid ground plane through a low impedance path.

27, 30,

31, 34

DAP

PAD

Power

Ground reference. The exposed pad at the center of the package must be connected to ground

plane of the board.

SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS

SDA

18

I/O, LVCMOS

Data input/output (bi-directional). Internally pulled high.

SDC

17

I, LVCMOS

Clock input. Internally pulled high.

CS

16

I, LVCMOS

Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When

pulled low, access to the equalizer SMBus registers are disabled. Please refer to System

Management Bus (SMBus) and Configuration Registers for detailed information.

Other

Reserv

19, 20

Reserved. Do not connect.

47,48

(1)

I = Input, O = Output

Copyright © 2007–2009, Texas Instruments Incorporated

Submit Documentation Feedback

3

Product Folder Links: DS32EV400