Symbol

Parameter

Conditions

Min

Max

Units

RD Delay from Address

15

ns

WR Delay from Address

15

ns

Data Hold Time

5

ns

Data Setup Time

15

ns

RD to Floating Data Delay

(Note 2)

10

20

ns

Master Reset Pulse Width

500

ns

Address Hold Time from RD

0ns

Read Cycle Update

29

ns

RD Strobe Width

40

ns

Delay from RD to Data

25

ns

Address Hold Time from WR

0ns

Write Cycle Update

29

ns

WR Strobe Width

40

ns

Duration of Clock High Pulse

External Clock (24 MHz Max)

17

ns

Duration of Clock Low Pulse

External Clock (24 MHz Max)

17

ns

RC

84

ns

WC

84

ns

BAUD GENERATOR

N

Baud Divisor

1

Baud Output Positive Edge Delay

ns

Baud Output Negative Edge Delay

ns

RECEIVER

Delay from Active Edge of RD to

78

ns

Reset Interrupt

Delay from Inactive Edge of RD

(RD LSR)

40

ns

to Reset Interrupt

Delay from READ to RXRDY Inactive

55

ns

Delay from RCLK to Sample Time

33

ns

Delay from Stop to Set Interrupt

(Note 1)

2

BAUDOUT

Cycles

Note 1

indication will be delayed 3 RCLKs Status indicators (PE FE BI) will be delayed 3 RCLKs after the first byte has been received For subsequently received bytes

these indicators will be updated immediately after RDRBR goes inactive Timeout interrupt is delayed 8 RCLKs

Note 2

Note 3

Note 4

For capacitive loads that exceed 100 pF the following typical derating factors should be used

AC Testing Load Circuit

TLC9426 – 22

4