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L138-FG-225-RC Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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L138-FG-225-RC Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
8 / 13 page Critical Link, LLC MityDSP www.CriticalLink.com MityDSP-L138F Processor Card www.MityDSP.com 29-AUG-2013 8 Copyright © 2013, Critical Link LLC Specifications Subject to Change Table 2 Signal Group Description Signal / Group I/O Description 3.3 V in N/A 3.3 volt input power referenced to GND. EXT_BOOT# I Bootstrap configuration pin. Pull low to configure booting from external UART1. RESET_IN# I Manual Reset. When pulled to GND for a minimum of 1 usec, resets the DSP processor. SPI_XXXX I/O The pins with an SPI_ prefix are direct connections to the OMAP-L138 pins supporting the SPI1 interface. The SPI1_CLK, SPI1_ENA, SPI1_MISO, SPI1_MOSI pins must remain configured for the SPI function in order to support interfacing to the on- board SPI boot ROM. For details please refer to the OMAP-L138 processor specifications. MII_XXXX I/O The pins with an MII_ prefix are direct connections to the OMAP-L138 pins supporting the media independent interface (MII) function. The MII pins provide multiplex capability and may alternately be used as UART, GPIO, and SPI control pins. For details please refer to the OMAP-L138 processor specification. MDIO_XX I/O The MDIO_CLK and MDIO_DAT signals are direct connects to the corresponding MDIO signals on the OMAP-L138 processor. These pins may be configured for GPIO. GP0_X IO General Purpose / multiplexed pins. These pins are direct connects to the corresponding GP0[X] pins on the OMAP-L138 processor. The include support for the McASP, general purpose I/O, UART flow control, and McBSP 1. For details please refer to the OMAP-L138 processor specifications. SATA_TX_P/N O These pins are direct connects to the OMAP-L138 SATA_TX differential Serial ATA controller pins. SATA_RX P/N I These pins are direct connects to the OMAP-L138 SATA_RX differential Serial ATA controller pins. GND N/A System Digital Ground. BX_Y_P.ZZ, BX_Y_N.ZZ IO FPGA I/O pins. These pins are routed directly to FPGA pins ZZ. The “X” indicates which FPGA bank the pin is allocated. The bank is either 0 or 1. The FPGA fabric supports routing pins in differential pairs, the Y_P and Y_N portion of the name indicates the pair number and polarity. The pins have been routed in pairs with phase matched line lengths. VCCO_X I FPGA Bank interface power input. These pins must |
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