Critical Link, LLC

MityDSP

www.CriticalLink.com

MityDSP-L138F Processor Card

www.MityDSP.com

29-AUG-2013

2

Copyright © 2013, Critical Link LLC

Specifications Subject to Change

The onboard OMAP-L138 processor provides a dual CPU core topology.

The OMAP-

L138 includes an ARM926EJ-S micro-processor unit (MPU) capable of running the rich

software applications programmer interfaces (APIs) expected by modern system

designers. The ARM architecture supports several operating systems, including Linux

and Windows Embedded CE.

In addition to the ARM core, the OMAP-L138 also

includes a TMS320C674x floating point digital signal processing (DSP) core. The DSP

core supports the freely provided TI DSP/BIOS real-time kernel. Users can leverage the

DSP to execute real-time compute algorithms (codecs, image/data processing,

compression techniques, filtering, etc.)

SO-DIMM-200 (DDR2 Connector)

System

Clocks

EMIFA (16-bit)

JTAG/Emulator

Texas Instruments

OMAP-L138

456-MHz ARM926EJ-

S ™ RISC MPU

456-MHz C674x VLIW DSP

(Many pins are multiplexed between peripherals)

JTAG

Header

8MB NOR Flash

(SPI interface)

For uBoot

bootloader

Xilinx

Spartan-6

FPGA

Up To XC6SLX45

CSG324 pkg.

Power

Management

Up To 256MB

mDDR Memory

16-bit wide

Up To 512MB

NAND Flash

8-bit wide

For root FFS

Boot

Config

1.2V

1.8V

2.5V

3.3V

JTAG

MMCSD 1

EMAC RMII

UHPI

uPP

LCD

VPIF I/O

FPGA I/O

Banks can be

1.8V, 2.5V, or

3.3V

Emulator

Header

Figure 1 MityDSP-L138F Block Diagram

Figure 1 provides a top level block diagram of the MityDSP-L138F processor card.

As

shown in the figure, the primary interface to the MityDSP-L138F is through a standard

SO-DIMM-200 card edge interface. The interface provides power, synchronous serial

connectivity, and up to 96 pins of configurable FPGA I/O for application defined

interfacing. Details of the SO-DIMM-200 connector interface are included in the SO-

DIMM-200 Interface Description, as shown below.