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GC5325SEK Datasheet(PDF) 2 Page - Texas Instruments |
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GC5325SEK Datasheet(HTML) 2 Page - Texas Instruments |
2 / 24 page GC5325 FUNCTIONAL BLOCK DIAGRAM BBin FB TX (LVDS) 18Pairs (Diff.) 19Pairs Input Interface 16 BBFR MFIO[19:18] 2 (Optional; additional 2LSBs) CFR Fractional Farrow Resampler Circular Limiter GC5325 JTAG MPUInterface RESETB SYNC 3 SYNC OUT INT UPDATA UPADDR OEB RDB WRB CEB TCK TRSTB TDI TMS TDO 16 10 4 BBCLK DPDCLK SYNCD (LVDS) (LVDS) BB PLL DPD PLL RealtoComplex (orBypass) Feedback Equalizer FeedbackNL Correction BulkInterpolation +Mixer Transmit Equalizer DPD ADC Interface DAC Interface CaptureBuffers BBClockDomain DPDClockDomain B0279-02 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGED DEVICE(1) TC 352-ball S-PBGA package, 27 mm × 27 mm –40°C to 85°C GC5325IZND (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 |
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