Preliminary Datasheet

Superior Multi-touch Capacitive Touch Screen Controller

AP386X

Aug. 2013

Rev. 1. 0

BCD Semiconductor Manufacturing Limited

5

Pin Description (Continued)

Pin Number

Pin

Name

Pin

Type

Pin Function

QFN-5×5

AP3860

QFN-6×6

AP3861

26

32

RSTN

I

Reset Low Active

Typically connect a resistor to VDD3V and a

capacitor to VSS. Low asserted and threshold at

condition. This pin should not be connected to any

27

33

WAKE/

GPIO0

I/O

Port 1.0 GPIO

8051 P1.0 GPIO. This pin can also be configured as

the wakeup pin from the host

28

34

INT/

GPIO1

I/O

Port 1.1 GPIO

8051 P1.1 GPIO. Open Drain output. This pin can

also be configured as the interrupt pin to notify the

host

29, 31 to 39

36 to 45

S0 to S9

I/O, A

Sensing Lines 0 to 9

These

pins

can

also

be

configured

as

I/O

bi-directional ports for test

-

46, 47

S10, S11

I/O, A

Sensing Lines 10 to 11

These

pins

can

also

be

configured

as

I/O

bi-directional ports for test

41

49

EP

Exposed Pad

“I/O” means input/output; “I” means input; “O” means Output; “P” means power; “A” means analog.

SCL and SDA Pin Description

Pull-up Enable

The pull-up enable for SCL and SDA is activated for AP386X, meaning that AP386X always has pull-up SCL

and SDA to VDD3V. During reset, SCL and SDA are as input pin. Moreover, if the pin connecting to the system

is floating, the internal pull-up will tie the pin to VDD3V (10k

). After AP386X is reset, SCL and SDA are

input until its corresponding register is configured.

Mode Selection

SCL and SDA can be used in I

open drain pin) by register setting.

Wakeup

SCL and SDA can be used for wakeup input signals in different mode. While I

protocol (SDA is low and SCL is high) on SCL and SDA is a wakeup signal to AP386X. While SPI mode is

enabled, an active low on the pin of SCL (serving as a slave select in SPI) is a wakeup signal to AP386X.

Moreover, a wakeup signal can be asserted by host from GPIO0.

INT/GPIO1

GPIO1 can be configured as open-drain or push-pull mode. Furthermore, GPIO1 pin has internal pull-up to

VDD3V (60k

) or VDD18 (10k) based on different register definition.