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WRF4824S-3WR2 Datasheet(PDF) 6 Page - RSG Electronic Components GmbH |
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WRF4824S-3WR2 Datasheet(HTML) 6 Page - RSG Electronic Components GmbH |
6 / 7 page The copyright and authority for the interpretation of the products are reserved by MORNSUN WRE_S-3WR2 & WRF_S-3WR2 2013.07.26-A/3 Page 6 of 7 OUTLINE DIMENSIONS,RECOMMENDED FOOTPRINT & PACKAGING TEST CONFIGURATIONS Input Reflected-Ripple Current Test Setup Input reflected-ripple current is measured with an inductor Lin and Capacitor Cin to simulate the source impedance. DC Cin Lin DC Load Oscilloscope Current Probe Lin(4.7 µH) Cin(220 µF, ESR < 1.0Ω at 100 KHz) DESIGN CONSIDERATIONS 1) Requirement on output load To ensure this module can operate efficiently and reliably, during operation, the minimum output load could not be less than 5% of the full load, otherwise output ripple maybe increase dramatically. If the actual output power is very small, please connect a resistor with proper resistance at the output end in parallel to increase the load, suppose to use the resistance of 5% rated power, or use our company ’s products with a lower rated output power. 2) Recommended circuit All the WRE_S-3WR2 & WRF_S-3WR2 series have been tested according to the following recommended test circuit before leaving the factory (see Figure 6). If you want to further decrease the input/output ripple, you can increase a capacitance-values properly or choose capacitors with low ESR. However, the capacitance of the output filter capacitor must be proper. If the capacitance is too big, a startup problem might arise. For every channel of output, provided the safe and reliable operation is ensured, the greatest capacitance of its filter capacitor must be less than the Max. Capacitive Load. General: Cin1: 5V&12V 100 μF 24V&48V 10 μF Cin2: 5V&12V 47 μF 24V&48V 1 μF Lin: 4.7 μH~12μH Cs: 10 μF~22μF Cout: 100 μF(Typ.) Lout: 2.2 μH~10μH Cd: 47nF/100V Single output Dual output +Vo 0V C out 6 7 8 Cs Ci n1 V in G ND 2 1 3 Vc R L in Ic D1 Cd Ci n2 +Vo 0V Cout 6 8 7 Cout Lout Lo ut -Vo Cin1 Vin G ND 2 1 L in 3 Vc R Ic D1 Cd C in2 (Figure 6) |
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