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QT2032 Datasheet(PDF) 8 Page - Applied Micro Circuits Corporation |
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QT2032 Datasheet(HTML) 8 Page - Applied Micro Circuits Corporation |
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8 / 220 page  8 AppliedMicro - Confidential & Proprietary Revision 5.11 QT2022/32 - Data Sheet: DS3051 Features Benefits Selectable LAN or WAN 1 mode operation Single module footprint to support LAN and WAN. 10GE, 10GFC and SONET 1 data rate support Compliant with multiple protocols Compliant to IEEE 802.3-2005 standard including WIS 1 , and XENPAK and XFP MSAs Industry standard operation Selectable XAUI lane ordering Flexible system card design Selectable 10G I/O polarity Accommodates polarity inversion Adjustable XAUI and 10G output amplitude Optimizes performance / power 9.6kB jumbo frame support Supports all Ethernet frame sizes 3.3V tolerant I/O Low speed I/O pins are compatible with 3.3V logic Optional ability to configure registers from an external EEPROM on powerup or reset Modify default register settings to customize device operation. Configurable polarity of low-speed CMOS I/O Flexible interface logic 25MHz MDIO operation Superior bus speed 1. QT2032 only QT2032 WIS Features WIS interface with extended SONET overhead processing Maximum flexibility in network design SONET overhead serial interface SONET overhead insertion and extraction Line-timing capability with optional VCXO interface Support synchronous transport Conditional (auto-linetiming) or forced line-timing operation Flexible operation VCXOONLY mode where the local SONET reference clock is eliminated Reduce system cost SONET-compliant jitter performance Compatible with SONET network timing requirements Module Features Integrated limiting amplifier with 20mVppD sensitivity Eliminates need for external limiting amp Internal LOS detector with option to use external LOS detector. Increased flexibility to accommodate design constraints. Support for dual rate module (10GE/10GFC) Two reference clock inputs for 10.3 and 10.5Gb/s in a single module Standard two-wire I2C interface to external EEPROM/DOM devices Reduced module cost I2C interface supports clock stretching by an external device Allows I2C operation with devices which use clock stretching for flow control Dedicated power-up reset pin No large capacitor required on the reset pin to the connector Two-byte I2C addressing capability to allow combined EEPROM+DOM memory in a single device Reduce number of devices on I2C bus Configurable LASI interrupt input for fast response to externally generated alarms Meet sub-10ms response time. Configure any register on powerup from EEPROM Customization of module System Card Features XFI compliant 10G serial interface XFP compliant XFP module access through MDIO Eliminates additional I2C bus to control XFP module 3 GPIOs, configurable as LED drivers with built-in Link and Tx/Rx Activity modes Easily drive faceplate LEDs with no additional firmware required Provides divide-by-64 output clock reference to XFP module Eliminates extra clock source on the board. Ability to access internal registers via the I2C interface Chip can be controlled entirely from I2C interface, eliminating need for MDIO access. Test and Diagnostics Multiple loopback modes Assists in system test and diagnostics PRBS and jitter generators and checkers Reduces need for expensive test equipment JTAG interface for Boundary Scan Standard design and manufacturing test and verification AC BSCAN IEEE1149.6 on XAUI I/O Standard design and manufacturing test and verification ‘Extended link monitoring' feature allowing far-end link status monitoring Link diagnostic capability XAUI 8B/10B decoder error counters on each lane Per-lane integrity checking, aids jitter tolerance testing Ability to selectively turn-off any XAUI output Full control of XAUI signal PCS scrambler/descrambler bypass mode Provides Test flexibility Register bits which mirror the state of the low-speed CMOS inputs Software monitoring of low-speed hardware I/O Frequency out-of-range (sync_err) indication Diagnosis of clock rate errors |
Similar Part No. - QT2032 |
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Similar Description - QT2032 |
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