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AT45DB321D-SU-SL955 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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AT45DB321D-SU-SL955 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
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3 / 52 page  3 AT45DB321D [DATASHEET] 3597T–DFLASH–11/2013 Table 1-1. Pin Configurations Symbol Name and Function Asserted State Type CS Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode (not deep power- down mode), and the output pin (SO) will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI). A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. Low Input SCK Serial Clock: This pin is used to provide a clock to the device, and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin are always latched on the rising edge of SCK, while output data on the SO pin are always clocked out on the falling edge of SCK. – Input SI Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input, including command and address sequences. Data on the SI pin are always latched on the rising edge of SCK. – Input SO Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin are always clocked out on the falling edge of SCK. – Output WP Write Protect: When the WP pin is asserted, all sectors specified for protection by the sector protection register will be protected against program and erase operations, regardless of whether the enable sector protection command has been issued or not. The WP pin functions independently of the software controlled protection method. After the WP pin goes low, the content of the sector protection register cannot be modified. If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore the command and perform no operation. The device will return to the idle state once the CS pin has been deasserted. The enable sector protection command and sector lockdown command, however, will be recognized by the device when the WP pin is asserted. The WP pin is internally pulled high, and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. Low Input RESET Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, and so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized, it is recommended that the RESET pin be driven high externally. Low Input RDY/BUSY Ready/Busy: This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during programming/erase operations, compare operations, and page-to-buffer transfers. The busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. – Output VCC Device Power Supply: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. – Power GND Ground: The ground reference for the power supply. GND should be connected to the system ground. – Ground |
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