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AT45DB321D-MU-SL955 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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AT45DB321D-MU-SL955 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 52 page 4 AT45DB321D [DATASHEET] 3597T–DFLASH–11/2013 Figure 1-2. Block Diagram 2. Memory Array To provide optimal flexibility, the AT45DB321D memory array is divided into three levels of granularity comprising sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level, and details the number of pages per sector and block. All program operations to the DataFlash device occur on a page-by-page basis. The erase operations can be performed at the chip, sector, block, or page level. Figure 2-1. Memory Architecture Diagram Flash Memory Array Page (512-/528-bytes) Buffer 2 (512-/528-bytes) Buffer 1 (512-/528-bytes) I/O Interface SCK CS RESET VCC GND RDY/BUSY WP SO SI Sector 0a = 8 pages 4,096/4,224 bytes Sector 0b = 120 pages 61,440/63,360 bytes Block = 4,096/4,224 bytes 8 Pages Sector 0a Page = 512/528 bytes Page 0 Page 1 Page 6 Page 7 Page 8 Page 9 Page 8,190 Page 8,191 Page 14 Page 15 Page 16 Page 17 Page 18 Sector Architecture Block Architecture Page Architecture Block 0 Block 1 Block 14 Block 15 Block 16 Block 17 Block 1,022 Block 1,023 Block 30 Block 31 Block 32 Block 33 Sector 63 = 128 pages 65,536/67,584 bytes Block 2 Sector 1 = 128 pages 65,536/67,584 bytes Sector 62 = 128 pages 65,536/67,584 bytes Sector 2 = 128 pages 65,536/67,584 bytes |
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